RISC-V vs ARM vs x86: The 2025 Silicon Architecture Showdown

• In mid-2025, x86 remains the top performer for legacy software and high-end workloads, with 64-core or 96-core Xeon/EPYC-class servers still setting the benchmark.
• Apple’s M-series SoCs, built on 8–10 core ARM64 designs and led by the M1 (2020) and M2 generations, demonstrate high performance-per-watt that rivals many x86 laptops.
• RISC-V’s open, modular ISA uses a small base with optional extensions (M, A, F/D, V) and allows custom instructions, with Ventana’s Veyron V2 offering up to 192 cores and RVA23 profiles improving cross-implementation compatibility.
• RISC-V is royalty-free and open by design, ARM licenses involve upfront fees and per-chip royalties (Qualcomm reportedly pays over $300 million per year), while x86 remains a closed, Intel/AMD-controlled ecosystem.
• X86 has the most mature software ecosystem, ARM is rapidly expanding into servers and desktops with Windows on ARM and AWS Graviton, and RISC-V is rapidly growing with Linux and Android support and official Ubuntu images for RISC-V.
• X86 security features include CET and SGX; ARM brings TrustZone, PAC, and MTE (with RME on newer cores); RISC-V is adding PMP and CHERI-derived security experiments like Keystone enclaves, with missions like NASA’s 8-core HPSC exploring RISC-V security.
• Mobile remains ARM-dominated, with nearly all smartphones using ARM-based SoCs, while RISC-V is gaining momentum in MCUs such as Espressif’s ESP32-C3 and wearables and Google plans Android support for RISC-V.
• In HPC and data centers, ARM is gaining share (Fugaku’s ARM A64FX, Graviton/Ampere in cloud), x86 remains strong in high-end workloads, and RISC-V is pursuing open accelerator roles (EPAC in Europe and Ventana’s cloud-focused cores) toward a future open-server ecosystem.
• Geopolitically, RISC-V’s openness is attractive to Europe and China as a way to reduce dependency on foreign IP, Arm and Intel have pursued alliances and foundry services to sustain ecosystems, and U.S. export controls continue to shape strategy.
• Industry trends point to heterogeneous multi-ISA systems and chiplet-based designs via standards like UCIe, enabling coexisting x86, ARM, and RISC-V cores on a single platform with improved software tooling and emulation to ease transitions.

The battle for computing supremacy is heating up in 2025, as three major CPU architectures – RISC-V, ARM, and x86 – vie for dominance. These instruction set architectures underpin everything from tiny IoT sensors to supercomputers. x86 has ruled PCs and servers for decades, ARM now powers virtually all smartphones (and even Apple’s Macs), and newcomer RISC-V is exploding in popularity as an open alternative. Each has unique strengths: x86 offers brute-force performance and a vast software legacy, ARM boasts efficiency and a mature mobile/embedded ecosystem, and RISC-V’s open design promises unprecedented flexibility and innovation eetimes.eu eetimes.eu. This report provides an in-depth comparison of the three architectures – covering technical foundations, performance, power efficiency, flexibility, licensing, ecosystem maturity, security, hardware implementations, and the latest trends as of mid-2025. We’ll also highlight expert insights, industry quotes, and upcoming products. The stakes are high: whoever leads in this “silicon architecture showdown” will shape the future of computing across mobile devices, cloud data centers, edge AI, and beyond.

Technical Foundations: RISC vs CISC and Design Philosophy

At a high level, the x86 architecture is the classic example of a CISC (Complex Instruction Set Computer) design, while both ARM and RISC-V follow RISC (Reduced Instruction Set Computer) principles. In practice, modern CPUs blur the lines – but the design philosophies still influence each architecture’s core.

• x86 (developed by Intel in the 1970s) is a CISC ISA with a rich, dense instruction set including many complex, legacy operations. Over the years, x86 has accumulated a lot of “baggage” for backward compatibility, from 16-bit real mode up through modern 64-bit extensions. This makes x86 chips powerful and versatile, but also bloated with legacy features. Modern x86 microarchitectures internally translate CISC instructions into simpler micro-ops (essentially RISC-like operations) for execution, mitigating some inefficiencies but at the cost of extra decoding logic tomshardware.com tomshardware.com. Intel even explored a simplified 64-bit-only x86 variant (dubbed x86-S) that would drop support for old 16/32-bit modes to streamline future chips tomshardware.com tomshardware.com. However, x86’s strength remains its robustness and raw performance, plus an unmatched legacy software base – you can still run decades-old PC apps on today’s x86 CPUs. This legacy support is both a blessing and a curse, giving x86 a huge ecosystem but also a heavier, less elegant architecture (hence higher power usage historically) dfrobot.com tomshardware.com.
• ARM (originally Acorn RISC Machine, later Advanced RISC Machine) was born in the 1980s as a pure RISC architecture. ARM instructions are fixed-size and relatively simple, enabling efficient pipelining and low power consumption – ideal for mobile and embedded use. Over time, ARM has added features (like Thumb compressed instructions, NEON SIMD, 64-bit ARMv8, etc.) and now in ARMv9 it incorporates advanced features like SVE2 vector processing and enhanced security, but it has remained a RISC-style load/store architecture at its core. ARM’s design philosophy prioritizes a high performance-per-watt ratio, which is why it dominates battery-powered devices dfrobot.com dfrobot.com. Compared to x86, ARM cores typically have a smaller, cleaner instruction set with far less legacy cruft. The trade-off is that historically ARM needed highly optimized software and couldn’t match x86’s peak performance in PCs – but that gap has closed fast (as Apple’s ARM-based M-series chips proved). ARM is proprietary; Arm Holdings licenses its ISA and core designs to chipmakers. Still, multiple companies can implement ARM cores, leading to a rich ecosystem of suppliers and innovations. In summary, ARM offers RISC efficiency with decades of ecosystem maturity, balancing performance and power extremely well for a broad range of devices.
• RISC-V is the newest player – a fifth-generation RISC architecture out of UC Berkeley (first introduced in 2010). It was designed from scratch to be clean, modular, and extensible, without the burden of legacy. The base RISC-V ISA has only a few dozen simple instructions, and then it defines optional extensions (for multiplication, atomic ops, floating-point, vectors, etc.) that designers can include as needed dfrobot.com dfrobot.com. This modular approach lets RISC-V scale from tiny microcontrollers up to super-scalar server processors by adding only the needed components. Importantly, RISC-V is open standard – the ISA is free and not encumbered by royalties. This harkens back to the ethos of open-source software, but applied to hardware. As a result, RISC-V chips can be designed by anyone without paying license fees, and custom instructions can be added for specific use-cases. The design philosophy emphasizes simplicity, energy efficiency, and freedom from legacy baggage dfrobot.com dfrobot.com. Industry veteran David Patterson (a co-creator of RISC-V and earlier RISC designs) noted RISC-V’s purity: it avoids the “complexity overhead” that x86 and even ARM accumulated, yielding a minimalist ISA that achieves performance through efficiency rather than sheer instruction count dfrobot.com dfrobot.com. In practical terms, RISC-V’s technical foundation gives it clean slate advantages – easier to implement and innovate on – but being new, it still trails in optimization and software support (for now).

Instruction Set and Flexibility: RISC-V’s instruction set is modular by design, which is unique. There is a small mandatory base (e.g. 32-bit integer ops) and many standard extensions (denoted by letters like M for integer multiply/divide, A for atomics, F/D for floating-point, V for vector/SIMD, etc.). Developers can also create custom extensions for special accelerators, making it highly flexible and customizable eetimes.eu eetimes.eu. ARM’s ISA is more monolithic – e.g. ARMv8-A for 64-bit includes a fixed set of features – though Arm does offer some flexibility via its architecture licensing (allowing companies like Apple or Qualcomm to design custom cores that implement the ARM ISA, and recently even limited custom instructions via its “Scalable Vector Extension”). x86 is the least flexible – it’s controlled entirely by Intel/AMD, and while it has numerous extensions (SSE, AVX, etc.), third parties cannot add their own. In terms of code density, all three have options for compressed instructions (x86’s variable-length instructions, ARM Thumb, RISC-V “C” extension), so memory footprint is comparable, though RISC-V’s designers aimed to be competitive on code size by learning from predecessors. In summary, RISC-V’s ISA is simplest and most extensible, ARM’s is rich but carefully managed, and x86’s is powerful but burdened by legacy complexity.

Performance and Power Efficiency

When it comes to raw performance, x86 traditionally led the pack in high-end computing – but ARM has closed the gap significantly, and RISC-V is fast catching up in certain domains. Here’s how they stack up in mid-2025:

• x86 Performance: Decades of refinement have made Intel and AMD’s x86 CPUs extremely powerful. High-end x86 chips (like Intel Core i9 or AMD Ryzen 9 for desktops, and Xeon/EPYC for servers) deliver top-of-the-line single-threaded speeds and multi-core throughput. They excel at heavy workloads that can exploit their aggressive out-of-order pipelines, large caches, and high clock speeds. For example, in server benchmarks, 64-core or 96-core x86 processors still often set the bar for absolute performance. However, this speed comes with high power consumption – x86 chips have historically been power-hungry, requiring robust cooling especially at peak load. Efficiency has improved (especially with hybrid architectures combining “performance” and “efficiency” cores as Intel now does), but x86 chips generally draw more power per operation than equivalent ARM designs dfrobot.com. In mobile or ultra-low-power contexts, x86 struggled (Intel’s attempts at smartphone chips failed largely due to power inefficiency). That said, in 2025 x86 remains king of legacy performance – for tasks like high-frequency trading, some scientific computing, and running older software, x86’s brute force and matured optimizations give it an edge. Yet, the energy cost is higher, and battery-powered devices have mostly abandoned x86.
• ARM Performance: ARM was once viewed as “slower but low-power,” suitable only for phones and embedded gadgets. That view is outdated. Today’s ARM-based processors can rival x86 in performance – while often beating it in efficiency. A watershed moment was Apple’s M1 chip (2020) and its successors (M2, etc.), which showed an ARM design outperforming comparable x86 CPUs in laptops/desktops at a fraction of the power draw dfrobot.com dfrobot.com. In 2025, Apple’s M-series SoCs (with custom 8–10 core ARM64 designs) continue to set a high bar for CPU performance-per-watt, outperforming many x86 laptop chips while sipping power. In the server arena, ARM chips like Amazon’s Graviton3 and Ampere’s processors offer dozens to 128+ cores, delivering competitive throughput with much lower TDP than Xeons. In fact, ARM’s efficiency is such that for the same power budget, an ARM server can pack more cores and often more total throughput – a key reason cloud providers are embracing ARM for scale-out workloads. That said, on absolute single-core performance, the fastest x86 cores (e.g. Intel’s Golden Cove or AMD’s Zen 4) still slightly edge out the fastest ARM cores (like ARM Cortex-X series or Apple’s cores) in some metrics, thanks to higher clock speeds and aggressive microarchitecture. But the difference is small, and ARM’s trajectory is steeply upward. Power efficiency is where ARM shines: its heritage in mobile means even high-performance ARM cores are optimized to do more work per watt. This makes ARM chips ideal for anything energy-sensitive – from phones (where ARM dominates) to data centers seeking better performance-per-dollar of electricity. In summary, ARM now offers near-peer performance to x86 in high-end computing, with superior energy efficiency. The entire Mac lineup switching from x86 to ARM is a testament: Apple demonstrated ARM chips can handle professional workloads traditionally reserved for x86, without sacrificing speed dfrobot.com.
• RISC-V Performance: RISC-V is the newcomer still proving itself on performance. Early RISC-V implementations were focused on microcontrollers and simple cores, so they lagged far behind x86/ARM in speed. However, this is rapidly changing. In the last couple of years, companies have debuted server-class RISC-V processors designed to compete with mainstream CPUs. For example, Ventana Micro Systems announced its Veyron V2 RISC-V chip with up to 192 cores, targeting cloud and AI workloads servethehome.com servethehome.com. While each RISC-V core may not yet match the IPC (instructions per cycle) of the very best x86/ARM cores, these chips leverage massive core counts and chiplet designs to achieve high throughput. Ventana claims competitive performance-per-watt for certain data center tasks, focusing on domain-specific acceleration alongside general cores servethehome.com. Another startup, SiFive, has developed high-performance RISC-V cores (the U8-Series, etc.) aimed at client devices and accelerators. The gap in single-thread performance is narrowing as RISC-V designs adopt techniques like out-of-order execution, large caches, and high clock speeds – essentially catching up on decades of architectural know-how. One advantage RISC-V has is the freedom to specialize: a RISC-V chip can include custom extensions for specific algorithms (e.g. AI processing, cryptography), potentially outperforming general-purpose cores in those areas. For instance, specialized vector and AI accelerators on RISC-V can yield huge speedups for those workloads. In summary, raw performance is not RISC-V’s strongest suit yet, but it’s improving fast. For many embedded and IoT uses, RISC-V cores are already “fast enough” with much lower cost or power. In high-end domains, 2025 marks the first wave of genuinely competitive RISC-V offerings (like multi-GHz, multi-core SoCs) coming to market eetasia.com eetasia.com. The consensus among experts is that RISC-V’s performance will continue to leap forward as more companies invest in advanced designs – potentially rivaling ARM and x86 in more areas within a few years. As one industry analyst put it, the conversation has shifted from “if and when” RISC-V will be viable to “when and how” it will be adopted, as the cores get stronger every generation eetasia.com.

Performance-per-Watt: If there’s one metric where ARM (and potentially RISC-V) beat x86 handily, it’s efficiency. ARM’s RISC design and decades of mobile tuning give it a clear edge in performance delivered per watt of power consumed. x86 chips have improved (especially with Intel’s new hybrid core approach and AMD’s 7nm/5nm process nodes), but they still often draw more power under load. This is why ARM-based servers can offer higher compute density within power-constrained environments, and why laptops using ARM chips (e.g. Apple Silicon Macs, or upcoming Windows on ARM devices) enjoy better battery life for similar performance. RISC-V designs, being lightweight and customizable, also show excellent efficiency in tailored tasks – many microcontroller-class RISC-V chips can run on tiny batteries for extended periods. As of 2025, ARM leads in energy efficiency for general-purpose processing, with RISC-V promising similar or better efficiency once its high-performance cores mature. x86 tends to be reserved for scenarios where absolute performance is needed and power is a secondary concern (gaming PCs, workstations, legacy software needs), or where years of x86-specific optimizations still give it an edge for certain applications.

Flexibility and Customization

One of the starkest differences between these architectures is how flexible and customizable they are:

• RISC-V: Unprecedented Flexibility. RISC-V’s open and modular ISA was explicitly designed for flexibility. Companies and even hobbyists can take the base ISA and add their own instructions or accelerators to optimize for particular workloads, without needing permission from a central authority. This has led some to dub RISC-V “the Linux of hardware”, because like open-source software, it enables a global community to collaborate and innovate on top of a common foundation. For example, a company making an IoT sensor chip can include just the RISC-V integer base and maybe a small multiplier – minimizing silicon area – whereas a company building an AI accelerator might add a custom matrix-multiply instruction to speed up neural networks. This ability to tailor the processor to the task is something neither ARM nor x86 offer to the same degree. As RISC-V International notes, the open ISA allows “greater control” and specialization that proprietary ISAs cannot match eetimes.eu eetimes.eu. A vivid illustration is how Nvidia uses RISC-V cores: Nvidia integrated dozens of custom RISC-V control processors inside its GPUs to manage tasks more efficiently than off-the-shelf controllers eetimes.eu. Such custom in-house tweaks would be hard if using locked-down ARM cores. RISC-V even permits alternate data widths (e.g. 32-bit, 64-bit, 128-bit variants) and has standard profiles for different domains (the recent RVA23 profile for applications includes vectors and virtualization for high-end use eetasia.com eetasia.com). The trade-off is that with great freedom comes risk of fragmentation – if everyone makes their own extensions, software compatibility could suffer. The RISC-V community is addressing this by ratifying standard profiles to ensure baseline compatibility eetasia.com. Nonetheless, in 2025 RISC-V clearly offers the most freedom to chip designers, which is a huge draw in sectors like custom accelerators, research, and any field where one-size CPUs don’t fit all.
• ARM: Configurable but Controlled. ARM sits in between – Arm Holdings provides a variety of IP cores and some configurable options, but ultimately Arm controls the ISA and its evolution. Large licensees can get an Architecture License, which lets them design custom microarchitectures that implement the ARM instruction set (Apple’s CPUs are a prime example, as are Qualcomm’s upcoming Oryon cores). But they cannot alter the ARM ISA itself – any new instruction or extension has to be approved and released by Arm Holdings. There have been limited programs for custom instructions (Arm announced a Custom Instructions extension for Cortex-M microcontrollers in recent years), but these are tightly scoped. In general, ARM offers a wide product portfolio – from tiny Cortex-M0 cores up to server-grade Neoverse cores – so customers pick a core closest to their needs and integrate it. This gives some flexibility in choosing the right core, but not in modifying its fundamental behaviors. That said, because so many companies license ARM, there is significant ecosystem diversity in ARM-based chips: e.g. one company might focus on adding a big GPU or NPU next to the ARM CPU, another might prioritize an ultra-low-power implementation. Arm’s approach could be described as “configured, not custom” – you can configure parameters (cache sizes, core counts, etc.) and choose from standard feature sets, but you generally cannot go wild with new ISA features. The benefit of this controlled flexibility is strong software compatibility across ARM chips and a guaranteed level of support from Arm Holdings for tools and IP. It also means ARM can enforce a level of consistency and quality (important for things like safety certifications in automotive). In summary, ARM provides moderate flexibility through its core varieties and architecture licenses, but it is still a proprietary platform with Arm as the gatekeeper of significant changes eetimes.eu eetimes.eu.
• x86: Least flexible (closed ecosystem). The x86 architecture is entirely owned and defined by Intel (and to a degree co-developed with AMD). No other entity can implement x86 CPUs from scratch without a license (and in practice, the only third-party x86 producer in recent years has been VIA/Zhaoxin in China via older licensing). This makes x86 a closed ecosystem – essentially a duopoly of Intel and AMD controlling its direction. If you want an x86 processor, you buy an Intel or AMD (or their few licensees’) chip. There’s no opportunity for customization by outside firms; even large companies like Google or Apple have not been able to make their own x86 chips (which is partly why Apple switched to ARM for more control). Intel and AMD do add new instructions (like AVX-512, or AMD’s recent AVX-512 competitors, etc.), but those come at the vendors’ discretion and often lead to fragmentation (e.g. some chips support a new extension, others don’t, causing software to have to detect capabilities). In the grand scheme, x86’s rigidity has one advantage: a program compiled for x86 will run on any x86 processor (with the same bit-width) going back many years – the platform is very stable. But it also means x86 cannot easily incorporate domain-specific innovations coming from the broader industry. Contrast that with RISC-V, where, for example, research groups have created experimental extensions for security and AI and can actually prototype them on real RISC-V silicon. With x86, innovation is limited to what Intel/AMD choose to do internally. This is a key reason many view RISC-V’s open model as a game-changer; as RISC-V International puts it, proprietary ISAs “stifled R&D progress” by locking the ecosystem, whereas an open ISA “facilitates collaborative solutions” and faster innovation eetimes.eu eetimes.eu.

In short, RISC-V offers maximum flexibility (open to customize), ARM offers curated flexibility (many options but within a controlled framework), and x86 offers consistency at the cost of flexibility (closed, “what you see is what you get”). Depending on the application, this can be a decisive factor – for instance, if a national program wants to develop a unique processor for supercomputing or military use without outside control, RISC-V is appealing; if a consumer PC maker just wants a reliable standard platform, x86 or ARM might be simpler.

Licensing Models: Open vs Proprietary

The licensing and business models behind these architectures are as different as night and day, and they carry big implications for cost, innovation, and even geopolitics.

• RISC-V – Open and Royalty-Free: RISC-V is an open standard, governed by RISC-V International (a nonprofit foundation). Using the RISC-V ISA does not require paying any licensing fees or royalties. Anyone can download the spec, design a CPU, and as long as it adheres to the spec, call it a RISC-V processor. This is akin to how anyone can use the Ethernet or Wi-Fi standards. The design implementations can be proprietary or open-source, but the ISA itself is open. This model lowers barriers to entry dramatically – startups, universities, and companies in developing countries can all create chips without the upfront costs that ARM or x86 would incur eetimes.eu eetimes.eu. It also fosters a community: companies share ideas on extensions, collaborate in working groups, etc., much like an open-source software community. However, open doesn’t mean no governance – the RISC-V foundation (headquartered in Switzerland for neutrality) manages ISA standardization to keep it from fragmenting badly eetimes.eu. The open model also means there’s no single company providing “official” RISC-V cores – instead, many vendors (SiFive, Andes, Tenstorrent, Alibaba’s T-Head, etc.) offer RISC-V IP or chips. This competitive market can drive down costs for customers. On the flip side, support and accountability are distributed – unlike with ARM, you can’t point to one entity that guarantees all RISC-V cores work; it’s up to implementers to ensure quality (though initiatives like RISC-V compatibility test suites and certification programs are emerging eetimes.eu). An important implication of RISC-V’s open license is seen in the geopolitical arena: countries or companies wanting independence from foreign IP control have gravitated to RISC-V. For example, the EU and China have both invested heavily in RISC-V as a way to boost domestic chip capabilities without relying on Arm (a UK/U.S.-linked company) or x86 (U.S.) eetimes.eu eetimes.eu. In fact, RISC-V International deliberately moved to Switzerland in 2020 to remain neutral and accessible to all, after concerns that U.S. export controls could restrict an ISA headquartered in the States dfrobot.com. Open licensing thus translates to both cost benefits and strategic autonomy. As one RISC-V advocate quipped, “No one can put an embargo on RISC-V – it’s open to everyone,” highlighting its appeal in an era of tech trade tensions eetimes.eu eetimes.eu.
• ARM – Proprietary Licensing: ARM’s model is proprietary but broad-based. Arm Ltd. (the company) owns the ARM ISA and all its designs. Companies must sign licensing agreements to use ARM technology. There are typically two types of licenses:
  • An IP Core License, where the customer uses Arm’s ready-made core designs (like Cortex-A78, Cortex-M55, etc.). They integrate these into their chips. This involves an upfront license fee and royalties per chip sold. The fee can be significant (hundreds of thousands to millions of dollars) and royalties might be a few cents to a few dollars per device depending on volume and core complexity. These fees contribute to the cost of ARM-based chips.
  • An Architecture License, where very large players (like Apple, Qualcomm, Samsung, etc.) license the ARM instruction set and design their own cores from scratch that execute ARM code. They still pay substantial fees for this, but it grants more freedom to differentiate. Even then, they owe royalties for using the ISA. A recent court case revealed some details: Qualcomm, for instance, pays over $300 million per year in royalties to Arm (around 10% of Arm’s revenue) tomshardware.com. That gives a sense of scale – these are not trivial costs for big vendors.
  The upside of Arm’s model is support and ecosystem. Licensees get extensive help – reference designs, software toolchains tuned for ARM, and assurance of compatibility. As EE Times noted, Arm license fees also buy you “support and liability coverage,” and access to a mature ecosystem of tools and vendors eetimes.eu. This has made ARM the safe choice for many – especially in conservative industries like automotive, where having a single throat to choke (Arm’s) if something goes wrong is comforting. However, the cost can be inhibitive for small players or low-margin devices. For example, a tiny IoT startup might find ARM’s licensing too expensive or cumbersome, making RISC-V attractive. Another aspect is control: using ARM means depending on Arm Holdings’ roadmap. If Arm decides to discontinue a core or not prioritize a feature, licensees have limited recourse. This tension surfaced recently in Arm’s dispute with Qualcomm over the latter’s custom-core plans (after Qualcomm acquired Nuvia). Arm sued to block Qualcomm’s custom ARM cores, arguing licensing violations, and even demanded Qualcomm destroy Nuvia’s CPU designs at one point tomshardware.com tomshardware.com. A jury ultimately sided with Qualcomm that their use was licensed tomshardware.com, but the conflict underscored that Arm as a supplier can exert significant control over its customers. It’s a proprietary dependency. In short, ARM’s licensing model offers a well-trodden path with strong ecosystem backing, but at a monetary cost and with strings attached. Companies often pay for the reliability and extensive existing software, and many are happy to do so – which is why ARM is in billions of devices. But the rise of RISC-V is partly a reaction to these costs and constraints.
• x86 – Closed and Exclusive: The x86 architecture’s licensing is the most restrictive. Essentially only Intel and AMD (and their close partners) can build x86 processors. Intel historically fiercely protected x86 IP – AMD’s x86 rights came from a 1980s technology exchange, and the two have cross-licensed patents since. A few others (Cyrix, VIA) once had licenses, but today it’s mostly down to Intel and AMD. If a third party wanted an x86 chip, they’d have to either use an Intel/AMD chip or get a special agreement (which is extremely unlikely). There’s no market in third-party x86 IP like there is with ARM’s cores or RISC-V cores. This exclusivity has led to the x86 duopoly in PC and server markets. The positive side is consistency – Windows PCs and software targeting x86 have a stable target, and Intel/AMD’s profits from x86 sales fund continuous R&D in the architecture. But the negative side is lack of competition and flexibility in licensing. If Intel raises chip prices or prioritizes certain markets, customers have limited alternatives except switching ISA entirely (which is what happened in mobile – nobody could license x86 cheaply for phones, so the industry went ARM). Moreover, the x86 model doesn’t easily allow customization or regional variants. It also means x86 innovations are tied to the business interests of two companies. For example, if neither Intel nor AMD focus on ultra-low-power microcontrollers, x86 simply won’t be present in that space (indeed, you don’t find x86 in tiny IoT nodes – it’s not offered there). From a cost perspective, system builders don’t pay a license fee for x86 (they just buy chips), but indirectly x86’s monopoly can command higher chip prices. The overall trend in the industry is away from such closed ecosystems, which is why many see x86’s licensing model as a relic of an older era. Open vs Proprietary Implications: The open RISC-V model is driving a democratization in chip design – encouraging new entrants, academic experimentation, and potentially faster innovation cycles eetimes.eu. It’s analogous to how open-source software (Linux, etc.) lowered costs and spurred creativity in software. ARM’s proprietary model, on the other hand, provides a more managed, stable evolution – innovation happens, but in a more centralized way and with profit motives for Arm Holdings shaping priorities. Both ARM and x86 being proprietary also has international implications: for instance, U.S. export controls can (and have) restricted high-end ARM and x86 technology access to certain countries. RISC-V, being open, is seen by some governments (like China) as a way to reduce dependency on foreign tech suppliers eetimes.eu nasdaq.com. This has prompted political debates – in late 2023, some U.S. lawmakers even considered whether to impose limits on RISC-V collaboration, fearing it could aid China’s chip ambitions nasdaq.com nasdaq.com. Executives in the RISC-V community argued that hobbling open collaboration would hurt Western innovation and just push RISC-V development offshore nasdaq.com nasdaq.com. Notably, Arm’s CEO Rene Haas commented that building a software ecosystem like Arm’s takes decades, and in his view, RISC-V still has a long road – he implied that any regulation slowing RISC-V would simply keep it “in Arm’s rearview mirror” longer nasdaq.com. In other words, the incumbents recognize that the open model is a real threat if it matures.

In summary, RISC-V’s open licensing means low cost and freedom at the potential expense of “one-stop-shop” support, ARM’s licensing means paying for a trusted ecosystem and support but accepting dependence on Arm’s terms, and x86’s model means you’re essentially buying a product with no ability to license or modify the tech yourself. This fundamental difference is a key factor for companies when choosing an ISA for a new chip project.

Ecosystem Maturity and Software Support

A processor architecture lives or dies by its ecosystem – the compilers, operating systems, software libraries, development tools, and community knowledge available. Here’s how our trio compare:

• x86 Ecosystem: Unquestionably the most mature in terms of general-purpose computing. Decades of dominance in PCs and servers means virtually all major operating systems, languages, and applications have x86 support (often as the primary target). Microsoft Windows has been built around x86 (and x64) since inception; most desktop software is x86-only or x86-first (though that’s slowly changing). Enterprise software stacks, from databases to cloud platforms, are deeply optimized for x86. The developer tooling for x86 is rich – every compiler (GCC, LLVM, MSVC, etc.) has top-notch x86 backends with many years of optimization work. There’s also a large talent pool of engineers familiar with x86 assembly, performance tuning, and security quirks. Importantly, backward compatibility is a huge asset: a program compiled for x86_64 in 2010 will run on an x86_64 CPU in 2025 without special effort. This means the accumulated software base is enormous. On the flip side, the x86 ecosystem is somewhat legacy-laden. For example, a lot of old code (including parts of Windows) still runs in 32-bit or uses legacy instructions that complicate modern support. But companies like Intel have invested in tools to ease transitions (like binary translation for moving 32-bit apps to 64-bit). In 2025, if you need to run something like Adobe Photoshop or a specific engineering tool, chances are the safest bet is an x86 machine (or an emulation of x86 on another system). Even with Apple’s shift to ARM, macOS retains x86 virtualization and emulation for running older apps, showing how deep the x86 software roots go. Overall, x86’s software ecosystem is vast and time-tested – a key reason it remains entrenched especially in corporate IT and certain professional fields.
• ARM Ecosystem: ARM’s ecosystem has grown exponentially since the smartphone revolution. Mobile OSes like Android and iOS are built for ARM by default, with millions of apps compiled for ARM chips (ARMv8-A 64-bit in modern times). On embedded systems, real-time OSes (FreeRTOS, Zephyr, ThreadX, etc.) and middleware support ARM Cortex-M and Cortex-R microcontrollers thoroughly. Linux has excellent ARM support – in fact, Linux kernel on ARM is well-maintained, and many modern network appliances and IoT gateways run ARM Linux. On the desktop/server side, the ecosystem historically lagged, but is now catching up quickly: modern releases of Windows 11 support ARM64 PCs (Windows on ARM) and can even emulate x86 applications for compatibility. While the Windows-on-ARM app ecosystem is not yet as rich, Microsoft’s continued push and Qualcomm’s upcoming faster ARM chips could change that. In the server world, all major Linux distributions have ARM builds (Ubuntu, Red Hat, SUSE all offer ARM64 editions). Cloud providers like AWS provide ARM instances (Graviton-based), and many cloud-native applications (databases, analytics engines, etc.) have been recompiled or optimized for ARM – AWS noted that many customers run common workloads on ARM instances to save cost and power. The development tools for ARM are very strong: GCC and LLVM have fully optimized ARM backends (largely thanks to mobile), and Arm provides its own toolchains too. ARM’s ecosystem also benefits from the huge number of developers familiar with it due to mobile app development. One notable area is Apple’s ecosystem: with macOS now on ARM, Apple brought along a huge desktop software ecosystem. Developers ported most Mac apps to ARM quickly, and Apple’s Rosetta2 translator smoothly runs most x86 Mac apps on ARM Macs, easing the transition. This proved that an ARM desktop ecosystem can thrive. One gap had been certain legacy enterprise apps and games not available on ARM, but even that is diminishing as compatibility layers and cloud options expand. Android’s ecosystem might soon intersect with RISC-V (as Google announced Android will support RISC-V as a platform), but until then it’s firmly ARM (with some x86 builds historically, but those are fading) dfrobot.com dfrobot.com. In summary, ARM’s software ecosystem is extremely robust in mobile/embedded, solid and growing in cloud/desktop, but still a step behind x86 in certain legacy desktop applications and games. The momentum, however, is clearly in ARM’s favor in anything new or power-sensitive.
• RISC-V Ecosystem: Being the newest, RISC-V’s ecosystem is the least mature, but it’s growing at breakneck pace – especially in the last couple of years. On the toolchain side, support is essentially there: GCC and LLVM both support RISC-V (with ongoing optimizations as the ISA extensions like vector get ratified). Linux has been ported to RISC-V and is part of the mainline kernel – you can boot a Linux system on RISC-V hardware today. In fact, multiple Linux distros (Fedora, Debian, openSUSE, etc.) have RISC-V editions or at least experimental support. In early 2023, there were milestone achievements like a RISC-V system running a KDE Plasma desktop on Linux, showing viability for basic PC use. However, many software packages needed for everyday use might require recompilation or tuning. The big news is Android’s support for RISC-V: Google announced that it is making RISC-V a “tier-1 platform” for Android, with official support rolling out (likely by Android 14 or 15) dfrobot.com opensource.googleblog.com. Google even demonstrated Android 13/14 running on RISC-V hardware and is working with industry partners to optimize it opensource.googleblog.com opensource.googleblog.com. This is huge because it means down the line, device makers could ship Android phones or tablets with RISC-V chips. Similarly, the RISE Project – a consortium including Google, Intel, Nvidia, Qualcomm, Samsung, and others – is actively working to accelerate the RISC-V software ecosystem (Android, Linux, compilers, etc.) opensource.googleblog.com opensource.googleblog.com. This level of industry collaboration is ensuring that within a couple of years, RISC-V will have first-class tool and OS support for many applications. Already, the IoT and embedded segment is well-served: FreeRTOS, Zephyr, and other lightweight OSes support RISC-V microcontrollers, and lots of development boards (HiFive, Arduino RISC-V boards, etc.) allow hobbyists to tinker. For high-end computing, RISC-V lacks some of the polished commercial software – e.g. you won’t find Adobe or AutoCAD on RISC-V anytime soon, and enterprise databases might not have official RISC-V ports yet. But in open-source and academic arenas, it’s active. The ecosystem challenge that remains is breadth: making sure all the libraries, drivers, and niche tools that people take for granted on x86/ARM are available on RISC-V. Efforts are underway – for instance, by late 2024 over 10,000 packages of popular software had been built for RISC-V Linux in some distro repositories. One advantage RISC-V has is that being new, it isn’t tied to any particular legacy OS – it can adopt modern paradigms from scratch. And because big players (like Intel and Nvidia) are invested, they are ensuring their software stacks (compilers, AI frameworks, etc.) support RISC-V. Nvidia, for example, uses RISC-V in its GPU controllers, so its toolchain includes support for that. The community aspect is also strong: universities globally are using RISC-V for teaching, meaning a new generation of developers is comfortable with it. RISC-V International highlighted that thousands of engineers and over 10 billion RISC-V cores in the market are driving rapid ecosystem growth riscv.org riscv.org. Still, as Arm’s CEO pointed out, building an ecosystem like what ARM has took decades, and RISC-V has a ways to go to replicate the depth of optimization and user-friendliness across all domains nasdaq.com. But given the trajectory – with Linux, Android, and major toolchains on board – it’s widely expected that RISC-V will achieve mainstream software parity in many areas by the late 2020s. Industry observers now say RISC-V software support has moved from theoretical to practical; as one SiFive exec noted, discussions have shifted to “when and how” companies will switch, implying confidence that the software stack will be ready when they do eetasia.com.

Ecosystem Maturity Summary: x86 is like a fully-grown oak tree – deeply rooted, broadly spread, but somewhat inflexible. ARM is a thriving forest – widespread, still growing into new areas (like PCs/servers), and benefiting from strong cultivation by Arm and partners. RISC-V is a fast-growing sapling – not as tall yet, but very vigorous and being fertilized by many contributors worldwide. From a developer’s perspective in 2025: if you write code for Linux or Android, you can target all three architectures (just recompile for each). If you have Windows code, x86 (and now ARM64) are your targets – RISC-V Windows isn’t here yet (though interestingly there have been rumors of Microsoft experimenting with RISC-V internally, nothing official). Toolchains like GCC/LLVM have largely erased the differences for cross-platform code. The real gaps are in proprietary software availability and the polish of ecosystem tooling (profilers, debuggers, etc.) on RISC-V. Those gaps are closing steadily as companies like Intel, Google, and Red Hat actively contribute to RISC-V support. A telling sign of ecosystem maturity is canonical platform support: for instance, Canonical announced official Ubuntu Linux images for some RISC-V development boards, indicating confidence that RISC-V can run a full OS reliably riscv.org riscv.org. Another sign is industry standards: RISC-V just ratified profiles like RVA23 to ensure that software can assume a certain set of instructions across all high-end RISC-V chips, which will smooth out compatibility issues eetasia.com eetasia.com. All in all, ARM and x86 still have the edge in sheer software breadth, but RISC-V’s ecosystem support in 2025 is robust enough for many real-world uses and on track to reach parity in the near future.

Security Features and Concerns

Security is a critical aspect of any architecture today, especially with threats like speculative execution attacks and the need for trusted execution environments. Each of our architectures has its own security features – and vulnerabilities:

• x86 Security: Being widely used, x86 was the first to face many modern attack vectors. Notably, the Meltdown and Spectre vulnerabilities (publicly revealed in 2018) hit x86 processors (Intel especially) hard – exploiting speculative execution to leak data across privilege boundaries. These hardware flaws forced Intel and others to issue microcode and software patches, often at performance cost. ARM cores were also affected by Spectre, but some variants of Meltdown were less effective on ARM; however, in the public eye x86 took the brunt of that storm. In response, both Intel and AMD have since added mitigations (stronger isolation in speculation, etc.). Apart from speculative attacks, x86 has traditionally supported a range of security features: NX bit (no-execute memory) was early adopted, address space layout randomization is standard, and both Intel and AMD have introduced forward-looking features. Intel’s SGX (Software Guard eXtensions) allows enclaves of secure memory for sensitive computations, aiming to protect data even if the OS is compromised. However, SGX saw some attacks and is not widely used outside niche applications. AMD’s approach, SEV (Secure Encrypted Virtualization), encrypts VM memory to protect it from other VMs or even from a malicious hypervisor – a big plus for cloud security. AMD also has SME (Secure Memory Encryption) for general memory encryption. Another security technology is Intel’s Control-Flow Enforcement Technology (CET), which introduces shadow stacks and indirect branch tracking to foil return-oriented and jump-oriented programming attacks. AMD has implemented similar concepts (e.g., Supervisor Mode Execution Prevention, etc., to block certain privilege escalations). In essence, x86 vendors have a toolbox of hardware security features built up over years, aimed at enterprise and consumer protections. However, the complexity of x86 (deep pipelines, speculative tricks) also opened a large attack surface, as Spectre showed. Going forward, Intel and AMD are focusing on designs that are “secure by design” (for instance, new microarchitecture that is less vulnerable to timing leaks). But one can argue that security is an ongoing battle for x86, patching legacy issues while adding new protections. The closed nature of x86 also means security auditing is in the hands of those two companies and external researchers, not a broad community as with open designs. On a positive note, legacy support can be dropped for security – for example, Intel’s proposed x86S would remove legacy modes partly to shrink the attack surface tomshardware.com. Overall, x86 chips in 2025 are reasonably secure if configured properly (virtually all have mitigations on by default now for known issues), and features like virtualization encryption give x86 an edge in certain cloud trust scenarios. But the architecture’s history means it will always carry some baggage.
• ARM Security: ARM, especially in the mobile space, pioneered some important security concepts. Most ARM processors include TrustZone, a hardware-enforced secure world that runs in parallel to the normal operating system. TrustZone (in ARMv8 and v9 for both A-profile and M-profile) allows sensitive code (like cryptographic keys, biometric authentication, digital rights management) to run in an isolated environment that the main OS can’t tamper with. This has been a cornerstone of mobile security – e.g., Apple and Android devices rely on TrustZone for things like secure payments and keystore. In recent ARMv9, Arm introduced the concept of Realm Management Extension (RME), which creates “realms” as a new secure execution environment for virtualization (sort of analogous to Intel SGX/AMD SEV, aimed at isolating VMs from each other and the hypervisor for cloud security). ARM has also implemented pointer authentication (PAC) and memory tagging in hardware. PAC adds cryptographic signatures to pointers to make it much harder for an attacker to execute code reuse attacks (by tampering with return addresses or function pointers) – Apple’s ARM-based CPUs famously use PAC to prevent many exploitation techniques. Memory Tagging Extension (MTE) helps detect memory safety bugs (out-of-bounds, use-after-free) at runtime by tagging memory allocations – a big step towards safer C/C++ usage. These features put ARM on the cutting edge of hardware-assisted security. Like x86, ARM was affected by speculative execution attacks (Spectre variants) – ARMv8-A’s high-performance cores had to implement mitigations. But simpler in-order ARM cores (like in microcontrollers) were immune by design to those timing attacks, which is worth noting – simpler RISC cores can inherently have fewer side-channels. One concern in ARM’s world is the complexity of the supply chain: ARM designs are in many devices with many variations, so ensuring all have up-to-date firmware/security patches is challenging (e.g., some cheap Android devices might not get timely fixes for ARM TrustZone vulnerabilities). However, the architecture itself is robust and benefited from learning from x86’s stumbles – many ARMv8+ cores were designed after researchers knew about speculative issues, so they could be engineered with mitigations from the start. ARM’s licensing model also means it’s easier to inspect the ISA for flaws (Arm often works with ecosystem partners on security standards). With ARM being so prevalent in safety-critical areas (cars, medical devices), there’s a strong focus on reliability and certifications (e.g., ARM has safety packages for automotive). In summary, ARM has a strong security feature set (TrustZone, Pointer Auth, etc.), and its inherent efficiency sometimes translates to simpler designs that avoid certain classes of vulnerabilities. The architecture isn’t immune (Spectre proved that, and some ARM cores had Meltdown-like issues too), but the industry has rallied to address those. ARM’s push into servers also brought more server-class security, like memory encryption options and parity with x86 on virtualization security. The trend with ARM is adding security without heavy performance penalties – e.g., pointer auth adds minimal overhead but thwarts many memory corruption exploits.
• RISC-V Security: As a newer architecture, RISC-V had the benefit of coming of age in the post-Spectre world. Its base design (being simple RISC) avoids some legacy pitfalls. But high-performance RISC-V cores will inevitably use speculation and thus could be vulnerable to similar timing attacks if not careful – it’s not the ISA that caused Spectre, but how modern CPUs are built. So RISC-V implementers are actively researching secure microarchitecture techniques. On the ISA level, RISC-V has been incorporating security-focused extensions: for instance, an optional Physical Memory Protection (PMP) mechanism (especially for embedded) that can enforce access control on memory regions (somewhat like an MPU for bare-metal secure enclaves). More ambitiously, there are projects bringing CHERI (Capability Hardware Enhanced RISC Instructions) to RISC-V, which is a research ISA extension for fine-grained memory protection (CHERI adds “capabilities” that include bounds and permissions, to eliminate many buffer overflow and pointer bugs). In fact, the UK’s Innovate UK program and others have been trialing CHERI-RISC-V prototypes. RISC-V’s openness also means it can adopt ideas from others freely – e.g., if pointer authentication is beneficial, RISC-V could add a similar extension (there is already a draft for cryptographic capability in RISC-V). Another example: open-source secure enclaves – projects like Keystone Enclave are creating an open framework for TrustZone/SGX-like functionality on RISC-V, allowing an enclave manager to isolate secure compute regions on a RISC-V system. Since RISC-V is modular, one can include an “N” extension for user-level interrupts or hypervisor mode to help implement isolation akin to TrustZone. It’s worth noting the open nature might aid security auditing: with RISC-V, the ISA spec and many core implementations are open, inviting academia and industry to scrutinize and formally verify aspects. For instance, multiple groups are working on formally verified RISC-V cores for critical systems. The flip side is that in 2025, RISC-V lacks some of the out-of-the-box polished security solutions that ARM and x86 have. There’s no official equivalent of TrustZone baked into every RISC-V core (instead, designers might implement MultiZone or other separation kernels using PMP). And features like vector crypto extensions (for accelerating encryption) are new and in progress on RISC-V, whereas ARM has had NEON crypto and x86 has had AES-NI for years. So RISC-V is catching up on security-specific extensions. One very practical security advantage of RISC-V is transparency: governments or companies worried about hidden backdoors may prefer RISC-V because they can inspect the RTL (if using open implementations like OpenHW cores or others) or at least know the ISA has no secret instructions. This has been cited by organizations like the CSIS, noting RISC-V enables a more collaborative and transparent approach to hardware, potentially enhancing trust in supply chains csis.org. For example, the European Space Agency’s ongoing RISC-V developments cite independence and auditability as reasons to go RISC-V for future spacecraft processors.

In terms of real-world security adoption: RISC-V is already in security-sensitive roles. Western Digital uses RISC-V in disk controllers and has developed an open security core (OpenTitan) with RISC-V for cryptographic functions. The NSA in the U.S. has explored RISC-V for certain applications because of its flexibility in adding custom cryptography. And notably, NASA’s next-generation Spaceflight Processor (HPSC), set to be used in future missions, is an 8-core RISC-V design by Microchip/Sifive – NASA chose RISC-V in part for its “good enough for NASA” reliability and the ability to customize for radiation-hardening theregister.com theregister.com. That endorsement speaks to confidence in RISC-V’s maturity and security for mission-critical use.

Overall, each architecture has robust security options, but none is invulnerable. x86 and ARM have a head start in deployed security features (and also in having been battle-tested by attackers). RISC-V’s youth means fewer known attacks in the wild – which could be an advantage temporarily, but as it gains popularity it will attract more adversarial attention. The encouraging part is that RISC-V designers are proactively building security in from the start, rather than bolting it on later. Meanwhile, ARM and x86 now converge on many similar security practices: encrypted memory, trusted execution zones, pointer authentication, etc. Where they differ is legacy exposure (x86 has the most, ARM moderate, RISC-V none) and openness (RISC-V allowing open review, x86/ARM being proprietary designs). Some foresee that security will be a major deciding factor – for instance, open government projects might lean to RISC-V for transparency, whereas commercial cloud providers might stick to ARM/x86 where they know the threat model and have vendor support. It’s also possible to use them in tandem: for example, an Intel CPU might use an internal microcontroller (Management Engine or Platform Security Processor) that could be RISC-V based, marrying both worlds’ security benefits. In fact, Apple is rumored to be shifting some of its internal management controllers in its SoCs from ARM cores to RISC-V cores, likely for efficiency and control theregister.com theregister.com – an intriguing development blurring the lines.

In summary, x86 and ARM have hardened themselves after past vulnerabilities and offer extensive security features (SGX/SEV, TrustZone, PAC, etc.), while RISC-V is rapidly implementing comparable features with the benefit of hindsight and openness. No architecture is inherently “more secure” in a vacuum – it depends on implementation – but the architectural decisions (like simplicity and modularity in RISC-V) can lend themselves to more straightforward security analysis.

Market Segments and Use Cases: Mobile, Servers, Edge, IoT, and Beyond

Each architecture has carved out niches where it excels, and areas where it lags. Let’s compare their strengths and weaknesses across key domains:

Mobile and Consumer Devices

Smartphones & Tablets: This domain is an ARM stronghold. Nearly 100% of smartphones today run on ARM-based SoCs (Qualcomm Snapdragon, Apple A-series, Samsung Exynos, MediaTek chips – all ARM). ARM’s low power design and high performance-per-watt, combined with its long-term investment in mobile GPU and modem integration, made it unbeatable here. x86 made an attempt (Intel’s Atom processors in some phones around 2012–2015), but they failed largely due to power inefficiency and lack of integrated LTE. Apple’s iPhone and iPad chips have always been ARM, and with Apple’s expertise they outclass even some laptop CPUs. ARM’s dominance in mobile is so complete that even Microsoft, for its Surface Pro X, turned to Qualcomm ARM chips to get cellular and battery life benefits for a tablet form factor. Consumers expect all-day battery life and slim form factors – ARM delivers that.

RISC-V in mobile is not yet in main application processors. However, it is making inroads in secondary roles within mobile devices. For instance, Google’s Pixel smartphones use custom Tensor Processing Units (TPUs) and other controllers; it’s plausible some controllers or power management units could be RISC-V. In 2023, Google publicly said it intends to get Android running on RISC-V and encouraged the ecosystem, which hints that future entry-level or specialized mobile devices might use RISC-V CPUs for Android dfrobot.com opensource.googleblog.com. There are already concept/prototype RISC-V smartphones showcased by enthusiasts, but none commercially mainstream. The first likely appearance will be in wearables and IoT consumer gadgets: RISC-V is very suitable for smartwatches, fitness trackers, wireless earbuds, etc. Qualcomm, for example, announced a collaboration to use RISC-V for wearables (smartwatch) chipsets in the near future opensource.googleblog.com. The ultra-low-power profile of RISC-V cores and the zero royalties make them attractive for cost-sensitive consumer electronics that aren’t running heavy apps.

PCs (Laptops & Desktops): Historically x86 territory (Windows PCs and traditional laptops are mostly Intel/AMD). However, this is shifting: Apple’s Mac lineup is now entirely ARM-based, which is a seismic change in the PC market. Apple proved that ARM can provide top-notch performance for desktops, not just mobile. On the Windows side, ARM-based laptops (using Qualcomm chips) exist but have been niche due to performance gaps. In late 2024/2025, Qualcomm’s new Oryon cores (from the Nuvia acquisition) are expected to significantly boost Windows ARM laptop performance, potentially taking a bite out of x86 laptop share. An industry prediction is that ARM will gain share at the expense of x86 in laptops, especially thin-and-light models, by offering better battery life and 5G integration eetimes.eu eetimes.eu. Microsoft optimizing Windows 11 for ARM is a strong signal of this trend. x86 still holds on in many gaming and high-performance laptops due to GPU coupling and inertia of software, but even gaming is seeing ARM encroachment (e.g., Apple’s M-series can run AAA games now, and developers are porting titles to macOS ARM). For desktops, beyond Mac, we might see Chromebooks or mini-PCs with ARM (there are already a few ARM Chromebooks). RISC-V PCs are in the embryonic stage – a company called Xcalibur announced a developer laptop called “ROMA” with a RISC-V CPU for 2023, mainly as a proof of concept. And organizations like Sifive have made high-performance RISC-V PC boards (HiFive Unmatched, etc.). But as one expert commented, RISC-V won’t be in Windows-based laptops in the immediate future eetimes.eu – the ecosystem and performance aren’t ready to challenge x86/ARM there yet. Instead, initial RISC-V laptops will target developers or specific niches (open-source enthusiasts, etc.) running Linux. It’s conceivable that by 2025’s end or 2026, we might see a basic consumer laptop with RISC-V for education or emerging markets (perhaps running a Linux-based OS or ChromeOS fork). However, mainstream consumers won’t encounter RISC-V in PCs just yet. In PCs, x86 still provides the broadest software compatibility (especially for Windows apps), and ARM now offers a compelling alternative for those prioritizing efficiency and integration (as Apple demonstrated).

Servers and Cloud Data Centers

This is a domain long ruled by x86, but it’s seeing the most upheaval:

x86 in Servers: Intel Xeon and AMD EPYC processors currently power the majority of servers worldwide, especially in enterprise and high-performance computing. They offer very high single-thread performance and up to 64–128 cores (AMD’s EPYC has 128 cores in the “Bergamo” variant using Zen4c). Years of optimization for data center workloads (virtualization support, memory bandwidth, I/O like PCI Express, etc.) make x86 servers the safe choice. And software like VMware, Oracle DB, etc., traditionally targeted x86_64. However, x86’s dominance in servers is eroding for the first time ever, primarily due to ARM-based servers. AMD and Intel are both responding by innovating (like adding AI accelerators on-chip, using 3D-stacked cache for performance boosts, etc.). Also, Intel’s manufacturing hiccups a few years back opened the door for alternatives, and power efficiency concerns in massive data centers made ARM attractive.

ARM in Servers: Over the past five years, ARM went from near-zero server presence to a significant player. Amazon’s AWS designed its own ARM server CPUs (Graviton series) and reports ~40% better price-performance vs comparable x86 for scale-out workloads, capturing a sizable chunk of AWS instances. Ampere Computing provides high-core-count ARM server chips (the 80-core Altra, 128-core Altra Max, and upcoming 192+ core AmpereOne), which are used by Oracle Cloud and others. Microsoft has reportedly tested ARM servers for Azure. Even in supercomputing, ARM made a mark: the world’s fastest supercomputer as of 2020, Fugaku in Japan, runs on Fujitsu’s 48-core ARM A64FX chips, demonstrating ARM’s capability in HPC with excellent floating-point and vector performance (it introduced the Scalable Vector Extension). ARM’s advantages in servers include lower power usage per core, high core counts, and often simpler thermals – all translating to cost savings at scale. As a result, many cloud providers and hyperscalers are adopting a hybrid strategy: use x86 for some tasks, ARM for others. One expert’s outlook for 2025 was that in markets outside China, we’d see limited switching of the main CPU in data centers to RISC-V (still too early), but fast adoption of RISC-V in subsystems for acceleration eetimes.eu eetimes.eu. For ARM, he suggested ARM will continue to gain share in data centers, especially cloud, at x86’s expense eetimes.eu eetimes.eu. This is already happening: some estimates say ARM-based servers could approach double-digit percentage of cloud CPUs by 2025. Another dimension is telecom and edge servers (like base station controllers, 5G infrastructure) – those often use ARM SoCs (like Marvell’s OCTEON or AWS’s Graviton at the edge) for power and integration benefits, further biting into x86’s pie.

RISC-V in Servers: On the horizon, RISC-V is positioning itself for future server and HPC roles, but as of mid-2025 it’s mostly in experimental or specialized use. That said, momentum is strong, particularly in regions like China where self-reliance is driving RISC-V server development. In China, companies like Alibaba (T-Head) and Huawei are actively exploring RISC-V for data centers to reduce dependence on imported IP. There are reports of prototype RISC-V server chips with respectable performance. Also, Western startups like Ventana and Esperanto are targeting accelerators and co-processors for data centers. Ventana’s Veyron V2, for example, is explicitly aimed at cloud providers wanting a customizable, domain-specific compute. It’s a chiplet-based RISC-V CPU that can scale to 192 cores per socket and integrate with specialized accelerators over the UCIe interface servethehome.com servethehome.com. The idea is a mix-and-match: standard RISC-V cores plus AI/ML accelerator chiplets, all in one package – a very modern approach that aligns with where cloud hardware is going (disaggregated, chiplet-based designs). The fact that Ventana’s CEO speaks of “serious traction” and customers investing tens of millions in their RISC-V solutions eetasia.com eetasia.com suggests that some niche but real deployments are not far off. Additionally, Europe’s EPI (European Processor Initiative) has a project for an accelerator called EPAC which is RISC-V based, intended to work alongside an Arm-based main CPU for HPC. This shows a hybrid model: x86 or ARM main processors, with RISC-V accelerators for specific tasks (like AI, data analytics). Over time, if those RISC-V accelerators keep growing in capability, one can envision all-RISC-V systems. But for mainstream enterprise servers in 2025, x86 and ARM are the choices; RISC-V is more likely to appear as a secondary engine (say, a smart NIC or storage processor, where RISC-V controllers handle offloaded tasks, which is already happening). By around 2030, we might see RISC-V main CPUs in data centers more commonly if the software ecosystem (Linux, virtualization, cloud middleware) proves out and performance meets needs. The interest is certainly there – government funding in the EU (270 million euros earmarked for RISC-V chips) and China’s massive investments point to eventual RISC-V server chips eetimes.eu eetimes.eu. As of 2025, though, one can summarize: x86 – still heavily used, especially for legacy enterprise apps and highest per-thread performance; ARM – rapidly growing for cloud and scale-out due to efficiency; RISC-V – emergent, with initial deployments likely as accelerators or in regions requiring open IP, poised for bigger role later.

IoT, Embedded, and Edge Computing

This is a broad category spanning tiny 8-bit microcontrollers up to moderately powerful “edge AI” devices.

Microcontrollers (MCUs): These are the small chips in appliances, toys, cars (numerous microcontrollers for sensors, etc.), typically running simple programs or a real-time OS. Traditionally, ARM’s Cortex-M series has dominated 32-bit MCUs, replacing older 8/16-bit proprietary ISAs (like 8051 or PIC) in many applications. ARM Cortex-M0/M3/M4 etc. are found in countless devices, with a huge ecosystem of vendors (STMicro, NXP, Microchip, Texas Instruments, to name a few). They are popular because of standardization (ARM’s well-known cores and instruction set) and the support ecosystem (software like Keil, IAR, etc., all support ARM MCUs). However, RISC-V is making major inroads in the MCU space. The allure is that smaller companies or even big ones can use RISC-V without paying royalties, which is very attractive in cost-sensitive MCU markets where margins are thin and volumes high. In fact, for simple 32-bit microcontrollers, RISC-V cores can often directly compete with ARM Cortex-M in performance and are cheaper. We’ve seen companies like Espressif (known for Wi-Fi/Bluetooth SOCs like the ESP8266/ESP32) move to RISC-V for their newer chips (ESP32-C3 has a RISC-V core, replacing a Tensilica core in previous versions). Chinese MCU vendors like GigaDevice, Allwinner, and others have introduced RISC-V microcontrollers. Even Western companies: Microchip has a RISC-V-based FPGA SoC line (PolarFire SoC) which includes RISC-V cores for the microcontroller part; Western Digital created a custom RISC-V core (SweRV) for use in storage controllers. By some estimates, billions of RISC-V cores are already shipping annually in IoT and embedded devices – one stat claims over 10 billion RISC-V cores in market by end of 2023 riscv.org riscv.org. In industrial and automotive embedded, RISC-V is attractive for similar reasons, plus the ability to customize for specific I/O or safety features. ARM isn’t sitting idle – it’s pushing new Cortex-M variants and trying to make licensing easier for IoT – but the momentum is with RISC-V. We might soon see RISC-V having a double-digit percentage of the microcontroller market (if not already, soon after 2025) because so many new entrants choose it. One example of community adoption: the popular Arduino platform released a board (Arduino Cinque and others) with RISC-V, and the Canonical Ubuntu Core is now supporting some RISC-V SBCs (single-board computers) which are essentially beefy microcontrollers with Linux riscv.org riscv.org. x86 is essentially absent in this space – you won’t find Intel or AMD cores in tiny MCUs (their lowest-end is Atom or old Quark, which never got traction in IoT due to power draw and cost).

Edge Computing / IoT Gateways: These are devices that sit between the sensors and the cloud – for example, a smart home hub, a factory IoT gateway, or on-premises AI inferencing boxes. They require more horsepower than a basic MCU and often run Linux. Here, ARM is very common (think of Raspberry Pi-class chips or Qualcomm’s IoT SoCs). ARM’s Cortex-A series or midrange SoCs fit well due to the combination of decent performance and low power. Many network routers, NAS devices, etc., run on ARM (often SoCs from Broadcom or Marvell). x86 does appear in edge when performance demands are higher and power is available – e.g., an edge AI server might use an Intel Xeon-D or Atom, especially if running complex analytics or needing to slot into existing x86-based software frameworks. Intel has positioned some Atom-class processors for edge (with extended temp ranges, etc.). But increasingly, specialized accelerators (often ARM-based or even DSPs) handle the heavy lifting at the edge for efficiency. RISC-V’s role at the edge could be significant in the future thanks to customization: an edge device doing AI could use a RISC-V core with custom tensor extensions to do inferencing more efficiently. Companies like Esperanto Technologies are building chips with dozens of RISC-V cores aimed at AI inference, explicitly targeting edge servers where power is limited but some serious compute is needed. Esperanto’s design (ET-SoC-1 with 1,000+ mini RISC-V cores) is a novel approach for energy-efficient AI, although commercial success remains to be seen. Also, because edge devices are often deployed in diverse environments, having an open ISA allows local players to build tailored solutions (for example, a European company could develop a RISC-V edge processor optimized for 5G base stations without relying on a U.S. supplier). In industrial IoT, real-time responsiveness and security are key; RISC-V can be adapted to specific real-time profiles and security certifications as needed. For now, though, ARM is the default for edge unless x86 compatibility is needed or extremely high performance. RISC-V is a rising alternative, likely to coexist by filling niches where its specific benefits (openness, customization, cost) matter.

Automotive: This spans from simple controllers (running your power windows or engine control unit) to advanced chips for autonomous driving. Historically, automotive ECUs (electronic control units) have used a mix – many are ARM-based MCUs or SoCs, some use specialized ISAs like Infineon’s TriCore or Renesas’s RH850 for specific real-time tasks. But ARM has been growing here, with Cortex-M and Cortex-R being used in safety-critical systems (Arm offers versions with ISO 26262 safety documentation). For infotainment and digital cockpits, higher-end ARM or even x86 chips appear (Tesla’s older Media Control Unit was an x86 Intel Atom; their newer ones are AMD Ryzen for infotainment, but the self-driving computer uses ARM cores and neural accelerators). Autonomous driving stacks often use custom silicon – Nvidia’s DRIVE platforms use ARM SoCs with big GPU/AI, Tesla’s FSD computer uses custom 12-core ARM-based SoC plus neural nets. Here, performance-per-watt is crucial due to limited car power and heat, so ARM has an edge. RISC-V in automotive is very promising in the long run. In 2022, a consortium of automotive giants (including Bosch, NXP, Denso, and others) formed to create OpenHW and other initiatives around RISC-V, and more recently companies formed a joint venture (mentioned as Quintauris GmbH in Europe) specifically to advance RISC-V in automotive and industry eetimes.eu. Their goal is likely to develop standard RISC-V cores that meet the strict functional safety and reliability needs of cars. Automotive lead times are long (chips designed now might go into cars in 2027+), but we can expect RISC-V to start appearing in new car models for certain subsystems (especially non-powertrain ones or ADAS modules) in coming years. The advantage is no single supplier risk (automakers worry about dependency on a single chip/IP supplier – RISC-V gives them more control). A challenge is ecosystem – autos require certified compilers, proven tools, etc., which ARM currently provides through its automotive programs. But with many players like Qualcomm (with Nuvia cores planned for automotive) and even ex-Arm China (whose former CEO founded a RISC-V startup) focusing on this, the support should materialize. In the immediate term, ARM remains dominant in automotive SoCs, x86 is rare (possibly for some high-end IVI/infotainment PCs or legacy reasons), and RISC-V is mostly in R&D/pilot phase. By 2030, we may see a far larger RISC-V presence as those development efforts bear fruit.

Edge AI & Specialized Accelerators: Many edge devices now incorporate AI accelerators (for image recognition, voice processing). ARM’s ecosystem includes NPUs (Neural Processing Units) and machine learning IP (Arm Ethos cores, etc.) that licensees can include. Nvidia uses ARM CPU + their GPU for Jetson edge AI modules. Google’s Edge TPU (Coral Dev Board) actually uses an NXP i.MX ARM CPU with a Google-designed ASIC for AI. But interestingly, some AI accelerators use RISC-V cores to orchestrate tasks. For example, the EdgeQ 5G base station chip (an upcoming product) combines a RISC-V controller with DSP blocks for signal processing. Many AI startups include RISC-V controllers in their accelerator cards (because it’s easy to integrate a free CPU core for general management on-die). The synergy of RISC-V with domain-specific silicon is a trend: you get a free control plane processor next to your custom accelerators, which is ideal. As a result, RISC-V is quietly ubiquitous as a companion core even in systems that might be marketed as “ARM or x86 solutions”. As of 2024, Nvidia was shipping on the order of a billion RISC-V cores a year inside its GPUs and SoCs (across all products) eetasia.com eetasia.com. That number shows how RISC-V can piggyback on the AI boom. So in edge AI appliances, one might have an x86 or ARM main CPU, but the AI board inside could have RISC-V cores in the background. Over time, if RISC-V cores become powerful enough, they could take on more of the main processing tasks as well.

High-Performance Computing (HPC) and Supercomputers

x86 in HPC: Most supercomputers historically used x86 CPUs (often combined with GPUs or other accelerators). For example, the US’s Frontier (exascale supercomputer) uses AMD EPYC CPUs plus AMD GPUs. x86’s maturity and great compiler support for scientific code (Fortran, etc.) made it a safe HPC choice.

ARM in HPC: The notable HPC success is Japan’s Fugaku, which took #1 on Top500 and uses ARM-based A64FX CPUs (no GPUs). It proved ARM can handle HPC workloads with high efficiency (it introduced the SVE vector extension which is great for dense math). Europe is also exploring ARM for HPC (the European Mont-Blanc project has looked at Arm, and Atos built an ARM-based supercomputer in France). With ARMv9’s SVE2, future ARM server chips can be very suitable for HPC as well. AWS’s Graviton is even being considered for some HPC in cloud contexts. Ampere’s upcoming chips might target HPC installations where power efficiency is key.

RISC-V in HPC: HPC centers are interested in open architectures to avoid vendor lock-in and to customize for their specific applications. The European Processor Initiative as mentioned has an accelerator based on RISC-V (EPAC) focusing on vector processing. The idea is to pair it with a general CPU in a heterogeneous supercomputer node. There’s also work in India (IIT Madras’s SHAKTI project) and in China (which reportedly is building some indigenous HPC chips due to sanctions) that involve RISC-V. While no top-ranked supercomputer runs purely on RISC-V yet, the groundwork is being laid. For example, in 2023 a prototype RISC-V supercomputing cluster was announced by the Barcelona Supercomputing Center using prototype RISC-V silicon. It’s expected that by the late 2020s, some national labs will deploy RISC-V supercomputers, especially if they want fully open hardware (for security or independence). One intermediate step is using FPGAs or reconfigurable RISC-V cores to test HPC kernels. In addition, China’s space agency and others are looking at RISC-V for HPC-like workloads in space, since open ISA allows radiation-hardening changes without needing foreign approval.

For now, x86 and ARM compete in HPC, with x86 slightly ahead due to incumbency and things like oneAPI, but ARM is proving itself (winning #1 spot, and Nvidia’s Grace CPU is ARM-based and targeting supercomputers especially for AI + HPC convergence). RISC-V is the dark horse – HPC folks love the idea of designing an ISA around their needs, and RISC-V gives them that freedom. The challenge is getting software (all those scientific libraries, etc.) optimized and stable on RISC-V. Given that HPC code often is open-source or at least highly specialized, porting is doable if there’s will and funding. So HPC might be one of the first places high-end RISC-V chips (with vector units, etc.) show their worth, albeit likely in a hybrid system with GPUs or other accelerators.

Strengths & Weaknesses Summary by Architecture

To crystallize the comparison, here’s a quick rundown of each architecture’s strengths and weaknesses across domains:

• x86 Strengths: Best established in PCs and servers, with unmatched legacy software support (especially Windows and enterprise apps). Extremely high single-thread performance on flagship CPUs. Wide availability of skilled developers and existing optimizations. In servers, offers strong backward compatibility and features like powerful virtualization and encryption (e.g., AVX-512 for heavy compute, SGX/TDX/SEV for security). Good for HPC currently due to mature compilers and dense performance, and for any use-case requiring decades of backward compatibility.
  x86 Weaknesses: Power efficiency is lower than ARM in most cases (makes it unsuitable for phones, challenging in power-limited servers). Architecture is burdened by legacy (complex to design and verify, more silicon area for decode, etc.). Closed ecosystem – lack of flexibility or alternative suppliers can mean higher costs and slower innovation. Fewer new entrants (only Intel and AMD driving it). Also, the high complexity has led to more frequent speculative execution vulnerabilities. In emerging areas like IoT and microcontrollers, x86 is nearly absent, ceding that entire category.
• ARM Strengths: Power-efficient performance – excellent performance-per-watt, making it ideal for mobile and embedded. Broad adoption means rich ecosystems: Android/iOS on mobile, growing Windows and Linux on other devices. Highly scalable – from tiny Cortex-M in a sensor to massive 128-core server chips – using essentially the same architecture principles. Licensing flexibility (many vendors and custom implementations) encourages competition and lowers chip costs (multiple ARM chip suppliers to choose from for a given need). Security features like TrustZone are widely deployed, enhancing its appeal in consumer and automotive. Rapidly gaining credibility in servers and PCs, with real-world success (Apple’s Macs, AWS’s cloud, etc.). In IoT and automotive, already deeply entrenched with a vast developer community.
  ARM Weaknesses: Still not as entrenched in legacy PC software – e.g., certain x86-only Windows applications or games might not run natively (though emulation bridges that somewhat). In servers, some enterprise software might not yet be optimized or certified for ARM, causing hesitation in adoption for conservative enterprise IT (though that’s diminishing yearly). Licenses can be expensive for startups or low-margin products; also, reliance on Arm Ltd means strategic risk (as seen in the Arm-Qualcomm legal spat – a reminder that Arm can enforce terms strictly) tomshardware.com tomshardware.com. While ARM is open to many licensees, the ISA is still proprietary, so ultimately Arm controls its development – if Arm were to change business terms (some fear post-IPO price hikes or different licensing models), it could impact the whole ecosystem. Additionally, customizing ARM beyond provided options is not possible – for highly specialized tasks, you must wait for Arm to release an appropriate core or extension, rather than implement it yourself.
• RISC-V Strengths: Ultimate flexibility and customization – can be tailored to any application, enabling domain-specific optimizations and innovation by anyone eetimes.eu eetimes.eu. No licensing fees – reduces cost per chip and lowers barrier for companies entering the chip business. A global open ecosystem fosters collaboration; many companies can contribute improvements (for instance, multiple companies worked together on the RISC-V vector extension to serve AI needs). Already proving itself in IoT and microcontrollers with competitive performance and ultra-low cost. The go-to choice for organizations seeking tech sovereignty (Europe, China investing heavily, as it frees them from reliance on foreign IP) eetimes.eu eetimes.eu. RISC-V designs can be very small and power-frugal when needed (great for tiny embedded), but also scale up – the modular ISA means no unnecessary baggage in a given implementation. Also, the ability to add custom instructions can yield better performance or efficiency for specialized tasks than general-purpose cores (for example, a RISC-V chip with a custom FFT instruction could outperform a standard ARM/x86 at FFTs). Community momentum is strong – there’s a sense of inevitability (“RISC-V is inevitable!” as the community says riscv.org) with big tech players involved and contributing to software support. In security, the openness and simplicity can aid verification and trust.
  RISC-V Weaknesses: Ecosystem immaturity – while improving fast, it still lags in out-of-the-box software support for many commercial applications (no Windows, and some Linux software might need porting). Lack of massive legacy base means any adoption requires proactive porting of software (though for new designs, this might be fine). Fewer high-performance proven designs – as of 2025, there’s no “RISC-V CPU” in a laptop or mass-market server to point to as a performance benchmark (the first might appear soon, but it’s early). This leads to a perception risk (“is it ready for prime time?”) for decision makers. Fragmentation concerns: if every vendor makes their own extensions, it could splinter the software ecosystem (efforts like RVA23 profile are addressing this by setting common standards eetasia.com). Also, support and liability are on the implementer – there’s no single vendor guaranteeing the core (unlike with ARM where if a core has a bug, Arm Ltd. assists licensees). Smaller companies may worry about that, though they can opt to license cores from well-known RISC-V IP companies to mitigate it. In very high-end performance (2025), RISC-V likely can’t match the absolute top x86/ARM designs until a few generations of catch-up (it’s on the way, but we have to see results). So for the highest performance needs right now – say a cutting-edge gaming PC or a top-10 supercomputer – RISC-V wouldn’t yet be the choice (but perhaps for top-500 supercomputer, maybe soon). Essentially, RISC-V’s weakness is being the new kid – lots of potential, but still needs to check all the boxes of a mature ecosystem to be a drop-in solution in every domain.

Each architecture thus has its domain leadership: ARM in mobile/embedded, x86 in traditional computing, RISC-V emerging in IoT and certain new verticals. They are increasingly overlapping though – e.g., ARM and RISC-V aiming at servers, x86 dabbling (unsuccessfully so far) in mobile. The competition will benefit consumers and developers as it drives all sides to improve. A comment from an industry veteran encapsulated it: different application areas will adopt RISC-V at different speeds based on ecosystem “stickiness” and incumbent inertia eetimes.eu eetimes.eu. For example, he noted smartphones will stay with ARM for now (incumbent too strong), whereas spaces like IoT, space, and some data center accelerators are already shifting to RISC-V where incumbents are weaker or specific advantages exist eetimes.eu eetimes.eu. Meanwhile, x86 will hold where its software lock-in is critical (many enterprise data centers still run legacy software). Over time, we can expect each architecture to refine its role – x86 might focus on high-end niches and backward compatibility, ARM on broad general-purpose and client devices, and RISC-V on customizable and emerging areas – with plenty of overlap and healthy competition in the middle.

Recent Trends and Current Events (2024–2025)

As of mid-2025, the tech industry is witnessing rapid developments around these architectures. Here are some of the notable current events and trends shaping the RISC-V vs ARM vs x86 landscape:

• ARM’s IPO and New Strategies: In September 2023, Arm Holdings had a successful IPO, underscoring investor belief in the ubiquitous role of ARM IP. Post-IPO, Arm is reportedly reevaluating its business models to drive growth – there’s talk of raising royalty rates or charging per-device fees (which has unsettled some partners) and of pushing further into markets like automotive and data center where it sees big upside. Arm’s CEO Rene Haas has publicly acknowledged RISC-V as a rising competitor but often in the same breath emphasized Arm’s huge software ecosystem as a moat nasdaq.com. Arm also engaged in an unusual PR move: in late 2022 it launched (and later took down) a website comparing ARM vs RISC-V (“Arm Flexible Access vs RISC-V: Get The Facts”), which seemed to be a defensive marketing campaign highlighting ARM’s advantages. The swift removal of that site (reportedly after internal pushback) hinted that even within ARM, the approach to RISC-V was contested – but it showed that Arm perceives RISC-V as enough of a threat to address it head-on reddit.com news.ycombinator.com. On the technical front, Arm rolled out its latest core designs (Cortex-A720, Cortex-X4 in 2024 for mobile; Neoverse V2 and next-gen E cores for servers). The Neoverse V2 (codename “Demeter”) is aimed at high-performance servers and is the core inside NVIDIA’s Grace CPU and Amazon’s Graviton3 – Arm claims significant per-core IPC improvements and continued focus on better performance-per-watt for cloud newsroom.arm.com techzine.eu. Arm is also working on Neoverse V3 and beyond, and a variant targeting HPC/AI with massive vector units. Upcoming smartphones (late 2024 into 2025) will likely feature the Cortex-X4 prime core, emphasizing that ARM is still the go-to for cutting-edge mobile CPUs. Another strategic trend: Arm is expanding beyond just selling IP – there are rumors it might design its own prototype chips to showcase capabilities (though not to sell commercially, as a reference design). All these moves aim to strengthen the ARM ecosystem just as alternatives rise.
• Apple’s Continued ARM Success: Apple’s transition to ARM (Apple Silicon) in Macs has been a resounding success, and by mid-2025 we expect the next generation (possibly “M3” chip on a 3nm process) to debut, further extending performance and efficiency. Apple’s chips have not only kept pace with x86, they’ve forced x86 PC makers to respond (for instance, we see ultrabook vendors touting battery life more aggressively now). Apple’s dominance in premium laptops has validated ARM for high-performance use. There’s also speculation Apple might eventually design its own server chips (for its data centers) based on ARM – nothing confirmed, but in the wake of AWS’s success, other large ARM licensees like Apple, Oracle, Microsoft could consider in-house ARM silicon for servers. On the RISC-V front, as mentioned, Apple is reportedly using RISC-V for certain internal controllers in its SoCs theregister.com theregister.com (possibly in the Bluetooth or storage controllers). A 2022 report by Semianalysis claimed Apple was replacing some of the small ARM cores with custom RISC-V cores in future iPhone SoCs theregister.com. If true, that’s a big psychological win for RISC-V (though those aren’t user-visible cores, it shows trust in RISC-V even within a top-tier chip). Apple hasn’t publicly commented on RISC-V, but it’s a member of RISC-V International. In any case, Apple’s success keeps ARM in the spotlight and puts pressure on both Intel (x86) and the broader PC software world to optimize for ARM.
• Intel’s Response and Embrace of Multiple ISAs: Intel, as the chief x86 proponent, has a dual strategy: continue advancing x86 (their roadmap with Meteor Lake, Arrow Lake in 2024, then Lunar Lake and beyond with new process nodes like 20A, 18A promises big efficiency gains), and at the same time, Intel is positioning itself as a manufacturing and IP partner for ARM and RISC-V. In a surprising but strategic move, Intel has become a significant ally to RISC-V: it joined RISC-V International, invested in RISC-V startups (like SiFive and others through its $1B foundry innovation fund), and is offering to manufacture RISC-V and ARM chips for clients via its Intel Foundry Services intc.com intc.com. Intel’s CEO Pat Gelsinger openly stated Intel wants to “support all leading ISAs” in its foundry intc.com. Intel realizes that even if x86 loses some ground, they can still make money producing others’ chips. In 2023, Intel announced a partnership with ARM to enable ARM core manufacturing on Intel’s 18A process by 2025, aimed at mobile SoC customers. For RISC-V, Intel has been working with companies like Andes, SiFive, and Ventana to ensure their IP runs well on Intel fabs intc.com. Intel is also building an open chiplet ecosystem (Universal Chiplet Interconnect Express, UCIe) where you could mix x86, ARM, RISC-V chiplets in one package, and it wants to be the go-to foundry for that modular future intc.com intc.com. On the x86 front, Intel had a notable incident: they proposed x86-S (64-bit only) to simplify future CPUs, but by early 2025 news broke that Intel abandoned x86-S plans after industry feedback steamcommunity.com hwcooling.net. This indicates that while dropping legacy sounds good, the ecosystem (especially PC OEMs and enterprise customers who rely on BIOS/16-bit stuff) wasn’t ready to break compatibility. So x86 will carry its legacy a while longer. AMD, meanwhile, is continuing to innovate with Zen microarchitectures; by mid-2025 AMD’s Zen 5 CPUs will likely be out (improving performance, possibly adding AI acceleration instructions as they signaled), and Zen 6 in development. AMD has also hinted at embracing heterogeneity – for example, rumors of an AMD “hybrid” APU with some ARM-based component for specialized tasks (one rumor codenamed “SoundWave” suggested AMD working on an Arm-based low-power core for a Microsoft Surface APU tomshardware.com tomshardware.com, but AMD hasn’t confirmed this). Whether or not AMD uses ARM, they are at least making sure to support non-x86 efforts in some ways – e.g., AMD is contributing to open-source for RISC-V in peripheral areas (like AMD’s driver team adding RISC-V support for certain graphics driver components riscv.org riscv.org). That shows even x86 companies are hedging bets in the RISC-V direction.
• NVIDIA and the AI Angle: Nvidia attempted to buy Arm in 2020–21, which would have been a game-changer, but that deal was blocked by regulators in early 2022. Post-acquisition, Nvidia pivoted to plan B: they became a Premier member of RISC-V International and have used RISC-V internally in many ways. Nvidia’s GPU controllers using up to 40 RISC-V cores is one example eetimes.eu. In 2022, Nvidia launched its Grace CPU, a data center CPU using ARM Neoverse cores, often paired with their GPUs for AI supercomputers (e.g., the combo Grace+Hopper system). So Nvidia now is in the CPU game with ARM, but also leveraging RISC-V for auxiliary processors. With the AI boom of 2023–2025, Nvidia is selling every chip it makes (mostly GPUs), but it’s interesting that its roadmap now includes CPU and possibly more integration. Industry watchers wonder if Nvidia might eventually design its own custom ARM cores or even RISC-V cores for AI-specific computing. The fact that Hyundai and Samsung invested $100M in Tenstorrent – a startup developing RISC-V-based AI chips – in 2023 riscv.org riscv.org suggests a belief that RISC-V can play a role in the AI chip arena, where customizing the architecture for ML workloads is key. AI accelerators often need tight coupling of general-purpose cores (for flexibility) and custom matrix units; RISC-V’s open approach is ideal there. It’s possible that future Nvidia products could integrate RISC-V cores in larger roles (for example, a future DPU – data processing unit – from Nvidia might use RISC-V as the main processor, given DPUs need many small cores for network tasks).
• China and Tech Sovereignty: A major trend influencing RISC-V vs ARM vs x86 is geopolitical tech decoupling. With the U.S. restricting China’s access to advanced x86 (and even advanced ARM designs via export controls), China has heavily invested in homegrown RISC-V as a way out. Chinese companies have introduced dozens of RISC-V chips for everything from appliances to servers. For instance, Alibaba’s T-Head semiconductor division has a line of RISC-V cores (the Xuantie series) and even demonstrated an Android running on their RISC-V SoC. Huawei, barred from making cutting-edge Kirin ARM chips for 5G phones due to sanctions, has reportedly looked into alternative architectures (though recently it used ARM cores again in a surprising new 7nm SoC, showing they still have some access). But in the longer term, China clearly sees RISC-V as a strategic technology where it can gain parity or leadership – it’s open, so no one can cut them off from the design, and they can contribute to it. RISC-V International’s move to Switzerland was partly to reassure Chinese members they wouldn’t be suddenly frozen out dfrobot.com. The Nasdaq article above highlights U.S. lawmakers’ concerns that “RISC-V could aid Beijing’s goals” nasdaq.com nasdaq.com – some in Washington even proposed limiting American firms from contributing to RISC-V open-source as if it were an export of tech. This is a contentious issue: RISC-V advocates responded that such restrictions would be shooting the U.S. in the foot, because American companies are among the biggest beneficiaries and contributors to RISC-V (e.g., Western Digital, Google, NVIDIA, and even military suppliers like Microchip). The CSIS report noted that RISC-V enhances the competitiveness of U.S. chip design firms by creating a low-cost platform for collaboration csis.org – essentially arguing the U.S. should embrace openness to stay ahead, rather than try to stifle it. As of 2025, no bans on RISC-V were enacted; instead, the U.S. is focusing on restricting chip manufacturing tools and such. But the conversation underscores that RISC-V’s rise is intertwined with national interests. We can expect China to pour resources into RISC-V advancement – e.g., by 2025 perhaps a Chinese exascale supercomputer with RISC-V accelerators might be revealed (they sometimes keep their supercomputers under wraps due to sanction fears). Also, Chinese consumer electronics companies (like Xiaomi or Alibaba) could surprise with a RISC-V based consumer product sooner than Western companies, since for them it’s a patriotic choice as well as economic.
• Community and Industry Collaborations: The RISC-V Summit events (annual conferences) have grown larger each year, with 2024’s North America Summit highlighting major milestones like the ratification of RVA23 application profile eetasia.com and multiple big tech keynotes. We saw companies forming alliances: e.g., in Europe, Ten European tech companies (including Bosch, Infineon, Siemens etc.) formed “EPI RISC-V” initiatives, in the U.S., DARPA funded open hardware programs using RISC-V, and India announced an ambition to create chips based on RISC-V for its digital programs (India’s first indigenous 64-bit core, Shakti, is RISC-V based). Even the Linux Foundation launched the RISC-V Software Ecosystem (RISE) project to coordinate software support across industry opensource.googleblog.com. All this collaborative activity suggests that RISC-V has rallied a diverse group who see value in an open hardware future. It’s somewhat reminiscent of the early days of Linux – many companies cooperating on a common core while competing in products. That bodes well for RISC-V’s longevity.
• Upcoming Product Roadmaps: A quick look at what’s expected or rumored for each:
  • x86: Intel’s Meteor Lake (2023) introduced a tiled (chiplet) design and integrated an AI accelerator (neural engine) on-chip; Arrow Lake (expected 2024) will refine that, and Lunar Lake (~2025) targeting low power, all using new Intel process nodes, aiming to reclaim efficiency leadership. AMD’s Zen 5 (late 2024) will power Ryzen 8000 and EPYC Genoa-X etc., promising IPC gains, and Zen 6 (~2025–26) in design, possibly moving to advanced 3D stacking, more AI instructions, and even more cores. Both are pushing DDR5, PCIe5/6, CXL interconnect in server – relevant as memory and interconnect are crucial to compete with new architectures. There’s also talk of Xilinx FPGA integration (for AMD) and custom AI cores (Intel’s Gaudi team) blending with x86 in future chips to add versatility. On the client, x86 is also being challenged by Chromebooks (mostly ARM now) and Apple (ARM), so Intel in particular is working on specialized mobile SoCs (with integrated 5G, etc.) to try and win back ground – e.g., the code-named Panther Lake around 2025 is expected to be a mobile-first architecture for Intel hardwaretimes.com hardwaretimes.com.
  • ARM: For mobile, the Cortex-X series (X4 in 2024, likely X5 by 2025) leads the high performance Android core arms race. We’ll see ARMv9 adoption become universal in new chips, bringing features like enhanced security and ARM’s new memory system architecture. On the server, ARM Neoverse roadmap: Neoverse V2 is out (NVIDIA Grace uses it), Neoverse V3 is expected to follow with further performance jumps to directly take on x86 in cloud/HPC by 2025 newsroom.arm.com techzine.eu. Ampere’s next chip after AmpereOne is rumored to scale beyond 192 cores perhaps with custom microarchitecture by 2025 – that could set a record for core count on a single socket, highlighting ARM’s core-scalability. Also, Qualcomm is a wild card: its Nuvia team was designing a server-class ARM core (before Qualcomm refocused them on PC/mobile). If Qualcomm revives server ambitions, we could see an ARM server chip from them too. Automotive ARM chips from players like NXP and Renesas with more AI capabilities are coming to handle autonomous tasks (they use ARM for general compute plus accelerators). Additionally, a trend is ARM in networking gear – Marvell’s Octeon 10 (ARM Neoverse based) is rolling out in 5G base stations, replacing MIPS/PPC legacy. We’ll likely see more of that by 2025 where every new piece of infrastructure has an ARM brain.
  • RISC-V: Many RISC-V chips slated for 2024/2025: Ventana’s Veyron V2 (as discussed) to ship in 2025 with customers building domain-specific servers eetasia.com eetasia.com. SiFive is launching the HiFive Pro P550 development board eetasia.com eetasia.com, which is like a mini PC for developers to run Linux on a fast RISC-V chip – a stepping stone to mainstream. Andes and other IP vendors are releasing higher-performance core IP – e.g., Andes announced its AX45 and AX65 series for Linux-capable apps and even some vector processing eetasia.com. On the GPU side, there’s interesting work on RISC-V GPUs (like a project called LibreGPU) so that a fully open hardware/software stack could exist. We might soon see RISC-V paired with open-source GPU in some niche (perhaps military or research). One must mention the Open Hardware aspect: the OpenHW Group, which develops open-source RISC-V cores (like the CORE-V family) announced upgrades that bring them closer to commercial core performance. This open core ecosystem means by 2025 there will be completely free designs available for mid-range RISC-V cores that anyone can fabricate (e.g., in 2024 they taped out an open 64-bit Linux-capable RISC-V core on GlobalFoundries 22nm). This can drastically broaden adoption in education and startups. Another upcoming product is from Alibaba’s T-Head: they demonstrated a 16-core RISC-V chip at 2.5GHz on 12nm, and hinted at a next-gen on 5nm approaching the performance of Arm Cortex-A76 class – those might go into cloud infrastructure in China. And looking at microcontrollers, Espressif has an upcoming ESP32-P4 (RISC-V dual-core at 400MHz) for IoT, which is significant as their chips often define IoT trends (they’re popular globally for DIY and commercial IoT). NASA’s RISC-V space processor (HPSC) should be delivered around 2025 for testing – an 8-core, fault-tolerant RISC-V by Microchip, likely to be used in Artemis moon missions and beyond theregister.com theregister.com. Its success will further validate RISC-V in aerospace and defense.

All these events paint a picture: the competition among RISC-V, ARM, and x86 is intensifying, driving rapid innovation. There’s a sense of an architectural realignment in progress – after decades of Wintel (Windows+Intel) hegemony, we now have a much more pluralistic environment. Each month brings headlines like “X company switches to RISC-V for Y product” or “ARM-based supercomputer sets record” or “Intel adds support for RISC-V in tool Z”. For consumers, the effects will be more choice (e.g., laptops with different CPU types to choose from) and hopefully better performance and value as these architectures push each other. For industry, it’s a time of adapting – software developers are learning to write and optimize code for multiple targets (hence frameworks like LLVM IR are appreciated, and languages like Java or .NET which are ISA-agnostic have renewed appeal in cross-platform scenarios).

One last current trend to note: software virtualization and emulation are smoothing differences. Apple’s Rosetta2, Microsoft’s x86-on-ARM emulation, and projects like Box64 for running x86 Linux apps on ARM/RISC-V, are making it easier to mix architectures without losing all legacy support. This means the barrier to adopting a new architecture is lower than it was a decade ago. If a RISC-V laptop can seamlessly emulate most x86 apps at decent speed, consumers might not care what ISA is inside. We see this with Apple – many users didn’t even realize their Mac switched ISA aside from noticing improved battery and performance, thanks to Rosetta. This trend may help RISC-V and ARM encroach on x86 territory with less friction.

Conclusion and Outlook

As of mid-2025, the rivalry between RISC-V, ARM, and x86 has evolved into a three-way race, each architecture bringing its philosophy to the forefront of modern computing. x86, the veteran, stands on its legacy of high performance and an immense software base, but it faces unprecedented pressure to innovate in efficiency and openness. ARM, the adaptive contender, has leveraged its efficiency to leap from mobile king to a legitimate challenger in PCs and servers, all while solidifying its hold on embedded and automotive fields. And RISC-V, the insurgent, has moved swiftly from academic curiosity to industry disruptor – proving that an open-source approach to hardware can galvanize global collaboration and spawn competitive products in record time.

In technical foundations, RISC-V’s clean-slate RISC design and modular extensions give it a long-term agility that bodes well as computing diversifies (from cloud to edge to specialized AI chips). ARM’s decades of RISC refinement and vast IP catalog offer a balanced mix of performance and efficiency, which is why it’s being embraced from smartphones to supercomputers. x86’s CISC heritage is no longer a deal-breaker due to modern microarchitecture techniques, but its baggage is evident – Intel’s own experiments with x86-S highlight the desire to shed some historical weight, even if the ecosystem isn’t ready to let go tomshardware.com tomshardware.com.

In terms of performance and efficiency, the playing field is far more leveled than in the past: ARM chips now prove that Watt for Watt they can outpace x86, and even go toe-to-toe in absolute performance in many cases dfrobot.com dfrobot.com. x86 is striving to catch up on efficiency (with new hybrid core designs and advanced process nodes) while leveraging its raw power and frequency scaling for an edge in specialized tasks. RISC-V’s performance, meanwhile, is sprinting ahead year by year, mainly driven by the realization that “good enough” cores coupled with massive parallelism or accelerators can achieve great throughput. We likely haven’t seen RISC-V’s true high-end potential yet – but early signs (like a 192-core cloud CPU servethehome.com or NVIDIA shipping RISC-V by the billion in GPUs eetasia.com) suggest it will surprise the skeptics sooner rather than later. As one RISC-V proponent put it, once vendors migrate and ecosystems develop, businesses will have “the perfect excuse to jump ship,” unleashing an “age of innovation and low-cost experimental design” in chips eetimes.eu eetimes.eu. That captures the optimism around RISC-V: that breaking free of proprietary shackles will usher in a new golden era of silicon creativity – much as open-source did for software.

Licensing and ecosystem differences also mean the competition is not purely technical but also economic and political. RISC-V’s open model is challenging the incumbent revenue models – Arm is adjusting how it licenses (perhaps charging per-device or per-period, knowing companies now have an alternative), and even Intel/AMD must justify the premium cost of their chips versus potentially lower-cost RISC-V or ARM solutions that meet the need. The result could be more favorable licensing terms or collaborations (we see Arm itself joining others in forming joint ventures to propagate its tech in open manners, and Intel partnering with RISC-V firms – unusual alliances a few years ago). On the geopolitical front, it’s clear that architectural independence is now part of national strategies: Europe funding RISC-V development for self-sufficiency eetimes.eu, China treating RISC-V as a cornerstone to avoid sanctions, the U.S. weighing how to maintain leadership in an open standards world – these all indicate that RISC-V vs ARM vs x86 is more than an engineering choice; it’s entwined with how countries and companies ensure they aren’t “held back by proprietary designers’ slow roadmaps” as EETimes put it eetimes.eu. In that sense, RISC-V’s rise could lead to a more democratized tech landscape, where no single corporation or country can monopolize CPU technology.

Meanwhile, security remains a double-edged sword: x86 and ARM have invested heavily in fortifying their architectures, learning from past flaws (with features like Intel CET, ARM PAC, etc.), while RISC-V gets to incorporate many of those lessons from the start. The coming years will test which architecture can best balance performance and security – a particularly pertinent question as more devices at the edge (think self-driving cars or implanted medical devices) require absolute trustworthiness. Open standards like RISC-V might accelerate security improvements by inviting broader scrutiny and innovation (for example, integrating CHERI capabilities for memory safety). But established architectures have the advantage of years of field testing and refinement, which RISC-V will gain only with time.

Looking ahead, we can anticipate some likely developments:

• Convergence and Hybrid Systems: It wouldn’t be surprising to see systems that integrate multiple ISAs in one solution – for example, a future laptop might have an x86 CPU for legacy compatibility and a RISC-V co-processor for efficient AI offload, or a server might have ARM main cores and RISC-V accelerators sharing the load. With chiplet-based designs and fast interconnects, mixing and matching core types could become mainstream, effectively ending any “one-ISA-to-rule-them-all” scenario. Intel’s foundry vision explicitly supports this heterogeneous future intc.com intc.com.
• Software Adaptation: The software industry is quickly adapting to a multi-architecture world. Development tools and languages are increasingly cross-platform. Cloud computing is abstracting away the underlying ISA (containers and orchestration don’t really care if the host is x86 or ARM). Microsoft’s .NET, for instance, runs on ARM now; Java runs everywhere; even gaming engines are being ported. This means the friction of switching architectures will keep reducing, enabling faster shifts if one architecture offers an advantage. For instance, if RISC-V hits a tipping point of being “good enough” and much cheaper, software houses could recompile and move quickly.
• ARM vs RISC-V Showdown: ARM and RISC-V seem set for a more direct clash, especially in embedded and IoT. ARM’s initiative to nudge smaller customers towards fixed packages (and perhaps raise prices) could inadvertently push those folks to RISC-V. There’s a notable quote from an ARM executive acknowledging RISC-V is great for low-cost controllers where you can just slot in an existing design cheaply news.ycombinator.com – a candid nod that in the microcontroller space, RISC-V offers a very compelling story on cost. Arm will likely focus on its ecosystem strength and support (the “you get what you pay for” argument). We might also see Arm responding by introducing more flexibility (maybe letting customers add minor custom instructions or open-sourcing some of its IP in part) – not confirmed, but competition can drive such moves.
• x86’s Future Role: x86 is not going away; its incumbency in PCs/servers and backward compatibility guarantee a long tail. But its role might shift more towards specialized, high-performance niches. AMD’s CEO Lisa Su has mentioned the concept of x86 and ARM coexisting, each suited to different workloads. We might see x86 more in high-end gaming, certain enterprise workloads that are hard to migrate, and perhaps in the very high single-thread performance space (since Intel and AMD will keep pushing clocks and IPC for certain applications like engineering software, simulations, etc.). Additionally, x86 could find life as x86-as-a-service: if eventually typical client devices become ARM or RISC-V, x86 might run in cloud instances to provide legacy compatibility on demand (kind of how IBM mainframe architecture still exists, but often accessed through virtualization). Intel and AMD are also expanding into GPUs, FPGAs, and custom accelerators to not rely purely on CPUs – showing they foresee a heterogeneous computing future and are repositioning accordingly (Intel with Habana/Movidius for AI, AMD with Xilinx FPGAs).
• Rise of Domain-Specific Architectures: With RISC-V lowering the barrier, we may see more domain-specific processors (for example, an open-source GPU ISA, or a VR/AR optimized CPU) that break the mold of one general-purpose ISA for everything. RISC-V itself might branch into profiles that are almost like separate niches (e.g., RISC-V for vector supercomputing vs RISC-V for microcontrollers share a base but look very different in practice). If done in a controlled way (so as not to fragment too wildly), this could yield big leaps in efficiency for certain tasks. The big question is whether such specialization will outpace the improvements in general-purpose cores with accelerators. But events like RISC-V International establishing standard profiles show an attempt to get the best of both worlds: specialization with some standardization.

In conclusion, mid-2025 finds the computing world at an inflection point. RISC-V, ARM, and x86 each have clear pathways to success, and their competition is a boon for the industry at large. For consumers and businesses, this means better performance, lower costs, and more choice. A quote from David Patterson, one of RISC-V’s creators, encapsulates the optimism: “I’m delighted that Intel…is now a member of RISC-V International,” he said, noting how historic it is that the pioneer of the microprocessor has embraced the open ISA future intc.com. It underlines that even the old guard sees the writing on the wall: openness and collaboration (exemplified by RISC-V) are driving the next era of semiconductor innovation. On the flip side, Arm’s CEO Rene Haas tempered the hype by stressing the difficulty of building ecosystems, implying RISC-V’s rise simply validates how valuable Arm’s own journey has been nasdaq.com. And as an Arm VP put it, the competition “helps us all focus and make sure we’re doing better” theregister.com. Indeed, each architecture is pushing the others to evolve – x86 is slimming down and integrating new tech, ARM is scaling up and out into every field, and RISC-V is accelerating standards and quality to meet enterprise expectations.

Ultimately, the “winner” may not be one architecture but rather the consumers and industries empowered by this technology abundance. We are likely headed for a heterogeneous world where all three (and perhaps others) find sustainable roles. The architectures might even cooperate within single systems in ways that blur the lines. It’s fitting that in 2025, the question isn’t “Which architecture will lead the way?” but rather “How soon will the open-standard approach achieve dominance, and in what form?” eetimes.eu eetimes.eu. The coming years will provide the answer, and if current trends continue, that answer could very well be sooner than anyone expected. The chip landscape is being reshaped before our eyes – a true silicon showdown – and regardless of which ISA ends up in your next device, it will be markedly better because RISC-V, ARM, and x86 are locked in this fierce but fertile competition.

Sources:

• Emily Newton, “Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way?” – EE Times Europe, Dec 2024 eetimes.eu eetimes.eu eetimes.eu
• Tobias Mann, “Arm execs: We respect RISC-V but it’s not a rival in the datacenter” – The Register, Sep 2022 theregister.com theregister.com
• DFRobot Blog, “Can RISC-V surpass X86 and ARM?” – Nov 2023 dfrobot.com dfrobot.com
• Tom’s Hardware, “Qualcomm wins legal battle over Arm — chipmaker didn’t violate Arm’s licensing” – Dec 2024 tomshardware.com tomshardware.com tomshardware.com
• RISC-V International, “RISC-V Highlights Progress and Market Traction” – Nitin Dahad, EE Times Asia, Nov 2024 eetasia.com eetasia.com eetasia.com
• Google Open Source Blog, “Android and RISC-V: What you need to know” – Oct 2023 opensource.googleblog.com opensource.googleblog.com
• Nasdaq/Benzinga, “RISC-V vs. ARM: How US-China Tech Tensions Could Redefine Chip Innovation” – Oct 2023 nasdaq.com nasdaq.com
• Intel Corporation Press Release, “Intel Launches $1 Billion Fund to Grow RISC-V and Foundry Ecosystem” – Feb 2022 intc.com intc.com intc.com
• Ian Ferguson (Arm executive) comments on EE Times, Dec 2024 eetimes.eu eetimes.eu
• Arm Newsroom, “Neoverse roadmap updates” – 2023 newsroom.arm.com techzine.eu
• Tom’s Hardware, “Intel optimizes slimmed-down X86S instruction set” – Sep 2024 tomshardware.com tomshardware.com
• RISC-V International Newsletter, “Message from RISC-V: RISC-V is inevitable!” – 2023 riscv.org