Santa Clara, California, April 22, 2026, 13:16 (PDT).
Taiwan Semiconductor Manufacturing Co introduced its A13 chip technology on Wednesday, outlining plans for smaller and faster processors without upgrading to ASML’s latest High-NA EUV equipment. The company remains committed to its existing EUV infrastructure, even as A13 targets production in 2029.
Timing is key here, with the AI rush pushing chipmakers to ramp up capacity quickly. Just last week, TSMC bumped up its revenue target for 2026 and signaled more capital outlays to keep up with AI orders; ASML, too, raised its 2026 forecast. On Wednesday, Santa Clara’s update suggested that costs and advanced packaging could weigh just as heavily as lithography as scaling continues.
TSMC described its A13 process as a smaller version of A14, squeezing out a 6% area reduction while keeping A14’s design rules in place—a move meant to speed up customer transitions. The company also rolled out N2U, a 2-nanometer variant expected in 2028, targeting a 3%-4% increase in speed or 8%-10% power savings compared with N2P.
EUV—extreme ultraviolet lithography—refers to the chipmaking technique that etches the minute patterns found inside top-tier processors. ASML’s high-NA (high numerical aperture) machines mark an upgrade, promising even finer detail. Back in February, ASML declared the tech production-ready for volume orders. Still, according to Bloomberg, TSMC’s Kevin Zhang stated the company doesn’t plan to deploy high-NA systems before 2029.
Zhang said he was “amazed” TSMC’s R&D group managed to keep scaling with existing EUV tools, holding off on the costly High-NA step for now. “Very expensive,” he said of the newer equipment. For his part, Chairman and CEO C.C. Wei described A13 as simply the next step in TSMC’s “reliable stream of new silicon technologies” — aimed at being ready for customers when demand comes. EE Times
Advanced packaging could end up being the bigger swing factor here. TSMC, for instance, is projecting that by 2028, its 14-reticle CoWoS—chip-on-wafer-on-substrate—will pull together around 10 large compute dies and 20 stacks of high-bandwidth memory, or HBM. Dan Hutcheson, vice chair at TechInsights, called the progress “bringing life back to Moore’s Law.” Business Wire
But that path isn’t without pitfalls. Reuters quoted analyst Ian Cutress, who noted TSMC still isn’t “addressing directly” the heat, expansion, and warping issues that come with scaling up to larger multi-die packages. If those technical hurdles end up being more stubborn than TSMC anticipates, the chipmaker may be forced to embrace newer lithography tech earlier than planned, or settle for slower progress. Reuters
The divide between Intel and TSMC is sharpening. Intel is calling itself the “first mover” on High-NA EUV, claiming this technology will boost resolution and scaling for its next foundry nodes. TSMC, on the other hand, is intent on squeezing more out of current EUV and betting on packaging for added performance. Newsroom
TSMC isn’t waiting on the roadmap—its packaging expansion is picking up speed. Speaking to Reuters this Wednesday, Zhang said TSMC aims to roll out CoWoS and other advanced packaging technologies in Arizona ahead of 2029. That’s while Amkor teams up with Apple and Nvidia on a packaging facility in Arizona projected to come online sooner.
TSMC sent a clear signal to major clients like Nvidia, Apple, and Google: it’s confident about advancing its roadmap for now, without jumping into purchases of ASML’s most expensive new equipment. ASML, after promoting High-NA as ready for mass deployment, now faces a reality check—adoption may be shaped as much by cost pressures as by technology.
